Need schematics and the hardware design particularly for the ECC support layout on the LS1043A-QDS. Any datasheets etc. to fully understand the layout and design for any related ECC interfaces and module(s) and an idea of what is memory is supported by the ECC: NOR, NAND, DDR4, etc?
Only DDR4 and NAND flash are supported by the ECC on the LS1043A-QDS board.
All information about the NAND flash ECC support can be found in the LS1043A Reference Manual, Chapter 25 Integrated Flash Controller (IFC).
The LS1043ARDB has the same Integrated Flash Controller (IFC) and ECC as the LS1043A-QDS, correct?
Is there anything else that needs to be added to the LS1043ARDB besides the four ECC lines and the 36-bit ECC DDR4 to use the IFC ECC on the LS1043ARDB?
We have designed the LS1043A-based board with the 36-bit DDR interface to be able to use the ECC feature, where the 32-bit is the memory itself and 4-bit is the ECC memory. We have added the four ECC lines. So as far as the board, that is all that is needed to support ECC on the LS1043A-RDB?
The NAND flash ECC support is a feature of the LS1043A device, not a board. Both LS1043A-RDB and LS1043A QDS have ECC support for NAND in the IFC controller of the LS1043A processor.
Four additional ECC lines are needed to support ECC on the DDR4. It is not related to the NAND flash ECC support.
I interpret your question as what is needed to add to the LS1043A-RDB board to support ECC on the DDR4.
Yes, the 36-bit DDR interface where the 32-bit is the memory itself and 4-bit is the ECC memory it is all you need in HW to support ECC on the DDR4.
We have all this designed as part of the custom LS1043ARDB. So all this is fine as far as the design.
In this question, I just needed to confirm we had everything designed correctly in hardware. You can close this question. Thanks.