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Why does ECC_ERR_INJECT[EMB,EIEN]=0b'11 cause a hard reset?

Question asked by Tracy Smith on Sep 13, 2018

Attempting to select mirror byte function for error injection.  ECC_ERR_INJECT[EMB, EIEN]= 0b'11

 

The default is 0b'00.

 

Why does writing to ECC_ERR_INJECT[EMB,EIEN]=0b'11 cause a reset?

 

root@ls1043ardb:~# devmem 0x1080E08 w 0x00030000

 [ 839.465065] Unhandled fault: synchronous external abort (0x96000210) at 0xff

 

Then the WDT is triggered and the board resets.

 

I had someone check the byte ordering and it looks fine. If I set the EMB only or the EIEN without EMB set (0x00020000 or 0x00010000), there is no hard reset. Only when I set both the EMB,EIEN (0x00030000) does it do a hard reset.

 

  • I can set both at the same time without a hard reset. Why is that?

 

  • What is the purpose of the EMB? 
  • Is the EMB a test bit to inject the error, even prior to reading and writing a word to a 0x5000 memory location?
  • ECC is supported on the LS1043ARDB, correct?
  • Are ARM ECC extensions required for this processor to support ECC?
  • Do I need to set the EMB to cause an ECC error when I write 0x55aa0000 to 0x5000?

 

22  EMB
ECC Mirror Byte.
0b - Mirror byte functionality disabled.
1b - Mirror the most significant data path byte onto the ECC byte.

 

23 EIEN
Error Injection Enable.
0b - Error injection disabled.
1b - Error injection enabled. This applies to the data mask bits, the ECC mask bits, and the ECC
mirror bit. Note that error injection should not be enabled until the memory controller has been
enabled via DDR_SDRAM_CFG[MEM_EN].

 

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