AnsweredAssumed Answered

LPC4370  GPDMA Transfer problem

Question asked by Ali Asadzadeh on Sep 9, 2018
Latest reply on Sep 12, 2018 by Kerry Zhou

Hi,

I wanted to just make some timer triggered DMA transfers, using Timer3 MAT0 as the trigger, here is my sample code, but I do not know what's going on that the timer would not make any requests into the DMA, my code for memory to memory Would works just fine. there is no DMA transaction!!!!

 

 

 

 

#include "LPC43xx.h" // Device header
#include "GPDMA_LPC43xx.h" // Keil::Device:GPDMA
#include "GPIO_LPC43xx.h" // Keil::Device:GPIO
#include "SCU_LPC43xx.h" // Keil::Device:SCU

uint16_t SPITXDummi[8]={0x1234,2,3,4,5,6,122,145};
uint16_t SPIRXDummi[8];

int main(void)
{

/* Confige timer 3 to make request 500ms each since we use 180MHz Clock */
LPC_TIMER3->MR0=90000000;
/* interrupt on MR0, reset timer on match 0 */
LPC_TIMER3->MCR = 0x0003;
/* toggle MAT0.0 pin on match */
LPC_TIMER3->EMR = 0x0031;
/* Reset Timer */
LPC_TIMER3->TCR = 2;


//Select Timer3 MR0 as DMA Request
GPDMA_PeripheralSelect (7, 0);

LPC_GPDMA->CONFIG = 1;
LPC_GPDMA->INTTCCLEAR = 0xFFFFFFFF;
LPC_GPDMA->INTERRCLR = 0xFFFFFFFF;
/* Enable synchro logic request */
LPC_GPDMA->SYNC = 0;

LPC_GPDMA->C0SRCADDR = (uint32_t) &SPITXDummi[0];
LPC_GPDMA->C0DESTADDR = (uint32_t)&LPC_TIMER3->MR1;//(uint32_t) &SPIRXDummi[0];

LPC_GPDMA->C0LLI = 0; // linked lists for ch0
LPC_GPDMA->C0CONTROL = 8 // transfer size (0 - 11) = 32
| (0 << 12) // source burst size (12 - 14) = 1
| (0 << 15) // destination burst size (15 - 17) = 1
| (2 << 18) // source width (18 - 20) = 32 bit
| (2 << 21) // destination width (21 - 23) = 32 bit
| (1 << 24) // source AHB select (24) = AHB 0
| (1 << 25) // destination AHB select (25) = AHB 0
| (1 << 26) // source increment (26) = increment
| (0 << 27) // destination increment (27) = no increment
| (0 << 28) // mode select (28) = access in user mode
| (0 << 29) // (29) = access not bufferable
| (0 << 30) // (30) = access not cacheable
| (1 << 31); // terminal count interrupt

LPC_GPDMA->C0CONFIG = 1 // channel enabled (0)
| (7 << 1) // source peripheral (1 - 5) = none
| (0 << 6) // destination request peripheral (6 - 10) = MAT0.0
| (5 << 11) // flow control (11 - 13) = mem to per
| (0 << 14) // (14) = mask out error interrupt
| (0 << 15) // (15) = mask out terminal count interrupt
| (0 << 16) // (16) = no locked transfers
| (0 << 18); // (27) = no HALT


/* Reset Timer */
LPC_TIMER3->TCR = 2;
LPC_TIMER3->TCR = 1; // enable timer
while (LPC_GPDMA->C0CONFIG & 1);// wait for the DMA to finish
LPC_TIMER3->TCR = 0; // disable timer


while(1)
{

}
}

Outcomes