I'm hoping someone can explain this behavior
K64 SPI set for 8 bit transfers, FIFO disabled, fed by DMA
Before the SPI process takes place -- as a note -- the CMD 16 bits of the SPI's Push Register is zero (0).
DMA is set for 8 bit transfers.
No CMD pushed into the SPI by the application.
The SPI transfer is started by setting DMA_SSRT
The Source pointer of the DMA channel is pointing to memory which holds an array of bytes increasing by 1.
Data array === 0,1,2,3,4,5 ..... 255
I use a logic probe to capture the actual SPI data and clock coming off the K64
Data on MOSI line is ==== 0,1,3,4,5 ... 255
Notice byte three (3) of the input data (byte value 2) is eaten and never appears on the MOSI line out of the K64.
NXP/Freescale has never really published good documentation on using DMA with SPI and only pushing DATA - never the upper 16 bits of COMMAND.
Is there any published documentation that can explain this behavior?
Any ideas as to why byte 3 is ALWAYS eaten and never appears on the output?
Note: the rest of the data is always transferred - independent of number of bytes -- the behavior is only at the start of the transfer and always byte 3