Found an error in the Clock Diadram tab on the LPC812 processor.

[alexanderandrij]

Found an error in the Clock Diadram tab on the LPC812 processor. It looks like UARTFRGMUL is confused (must have a range of values from 0 to 255, but only 255 can be entered) and UARTFRGDIV (must have a fixed value of 255, but it does not). It should be exactly the opposite. To whom to address this problem?

[marek_neuzil]

Hi Alexander,

I have checked the clock model against the reference manual but it seems that the clock model is correct. The clock model implementation represents the fractional scale factor of the divider that is described in the reference manual. The MULT value represent the numerator of the fractional divider and the DIV value represent the denominator value.

The UART_fractional_divider_output_frequency = UARTCLKDIV_output_frequency / (1 + MULT/DIV) =  UARTCLKDIV_output_frequency / ((DIV + MULT)/DIV) = UARTCLKDIV_output_frequency / ((256 + MULT) / 256)

Note: The only allowed value of the DIV is 256 (or 0 when fractional part is disabled).

Therefore the scale factor of the fractional divider  = (256 + MULT) / 256

i.e. divider = 256 + MULT, multiplier = 256.

See also the reference manual of the LPC812 (UM10601)

I understand that the clock model of this fractional divider is confusing but the model is correct. We will try to improve the representation of this UART fractional divider.

I have also checked the generated code and it seems that the register UARTCLKDIV (the DIV bitfield) is not initialized by the value of the denominator (256) in the generated initialization code. I will report this issue to the responsible development team.

Best Regards,

Marek Neuzil