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S32k116 CAN Channel0 Interrupt not Triggered

Question asked by ANAND PALANI on Jun 6, 2018
Latest reply on Jun 7, 2018 by Alexandru Nan

Hello, 

          I am trying to configure the OR'ed Message buffer interrupt for CAN channel 0 using S32k116 EVB but the ISR been never hit with this configuration. Observed during both scenarios message transmission adn reception.Please look in my CAN module configuration and IRQ initialization let me know if i am missing something.

 

void NVIC_init_CAN0_IRQs (void)
{
S32_NVIC->ICPR = 1 << CAN0_ORed_0_31_MB_IRQn; /* IRQ11-FlexCAN ch0: clr any pending IRQ*/
S32_NVIC->ISER = 1 << CAN0_ORed_0_31_MB_IRQn; /* IRQ11-FlexCAN ch0: enable IRQ */
S32_NVIC->IP[CAN0_ORed_0_31_MB_IRQn] = 0x0A; /* IRQ11-FlexCAN ch0: priority 10 of 0-15*/
}


void FLEXCAN0_init(void) {

uint32_t i=0;

PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */
CAN0->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */
CAN0->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKSRC=0: Clock Source = oscillator (8 MHz) */
CAN0->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/
while (!((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {}

CAN0->MCR |= CAN_MCR_IRMQ_MASK; /* IRMQ=1: Individual RX masking and Queue enable */
/* Good practice: wait for FRZACK=1 on freeze mode entry/exit */
CAN0->CTRL1 = 0x04DB0006; /* Configure for 500 KHz bit time */
/* Time quanta freq = 16 time quanta x 500 KHz bit time= 8MHz */
/* PRESDIV+1 = Fclksrc/Ftq = 8 MHz/8 MHz = 1 */
/* so PRESDIV = 0 */
/* PSEG2 = Phase_Seg2 - 1 = 4 - 1 = 3 */
/* PSEG1 = PSEG2 = 3 */
/* PROPSEG= Prop_Seg - 1 = 7 - 1 = 6 */
/* RJW: since Phase_Seg2 >=4, RJW+1=4 so RJW=3. */
/* SMP = 1: use 3 bits per CAN sample */
/* CLKSRC=0 (unchanged): Fcanclk= Fosc= 8 MHz */
for(i=0; i<128; i++ ) { /* CAN0: clear 32 msg bufs x 4 words/msg buf = 128 words*/
CAN0->RAMn[i] = 0; /* Clear msg buf word */
}
for(i=0; i<16; i++ ) { /* In FRZ mode, init CAN0 16 msg buf filters */
CAN0->RXIMR[i] = 0; /* Don't Check for message IDs, receive all messages */
}
CAN0->RXMGMASK = 0x1FFFFFFF; /* Global acceptance mask: check all ID bits */
CAN0->IMASK1 = 0xFFFF; /*Configure all Interrupts*/
CAN0->RAMn[ 4*MSG_BUF_SIZE_CAN1 + 0] = 0x04000000; /* Msg Buf 4, word 0: Enable for reception */
/* EDL,BRS,ESI=0: CANFD not used */
/* CODE=4: MB set to RX inactive */
/* IDE=0: Standard ID */
/* SRR, RTR, TIME STAMP = 0: not applicable */
CAN0->RAMn[ 4*MSG_BUF_SIZE_CAN1 + 1] = 0x301 << CAN_WMBn_STD_ID_SHIFT;


CAN0->RAMn[ 5*MSG_BUF_SIZE_CAN1 + 0] = 0x04000000; /* Msg Buf 4, word 0: Enable for reception */
/* EDL,BRS,ESI=0: CANFD not used */
/* CODE=4: MB set to RX inactive */
/* IDE=0: Standard ID */
/* SRR, RTR, TIME STAMP = 0: not applicable */
CAN0->RAMn[ 5*MSG_BUF_SIZE_CAN1 + 1] = 0x303 << CAN_WMBn_STD_ID_SHIFT;

CAN0->MCR = ( CAN_MCR_IRMQ_MASK | CAN_MCR_SRXDIS_MASK | 0x0000001F); /* Negate FlexCAN 1 halt state for 32 MBs */
while ((CAN0->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {}
/* Good practice: wait for FRZACK to clear (not in freeze mode) */
while ((CAN0->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {}
/* Good practice: wait for NOTRDY to clear (module ready) */

}

 

Thanks in advance!

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