In very need for Assistance...!
- Platform: S32R274, DSPI MCAL Code and rest of application is Legacy.
1) During context restore from ISR to Function Context, somewhere the CPU GPRs and LR(Link Register) are being loaded with false return address instead of actual return address. Also as a side effect the LR and IP points to this undesired address (some function say Function5() ) causing infinite looping.
1) A S32R274 based legacy project has a SPI Slave.
2) SPI MCAL is configured, generated, integrated on to this Legacy-Code. (Only SPI is MCAL)
3) Spi_AsyncTransmit( ) is called and the TX_FIFOs are Loaded and data is transmitted. (Total 8 Bytes (Channels) in a Job, Sequence) and for each byte Tx the below TCF (Transmit Completion ISR) is called.
4) The Rx'ed data is copied to Application buffers in "SPI TCF ISR" i.e Spi_Dspi_IsrFifoRx().
/* ISR Function Body Example */
Spi_Dspi_IsrFifoRx(); /* Load Rx FIFO content to Application buffer.
/* End of ISR Function Body */
5) At the end of ISR Body i.e during execution of Prolog i.e ' } ' (Reverting the context), the CORE-1 CPU Registers are being loaded with false address which is further loader in to the LR (Link Register) and the function is unable to return to the actual caller function but instead Branches with Link to undesired function. (blr instruction)
6) And then it stays here with reason that: LR (Link Register) and IP (Instruction Pointer) points to the same address.
(Q) What might cause the LR (Link Register) to get loaded with "Undesired FunctionAddress" than with address of actual function to where the control shall RETRUN after ISR Context is finished.
(Q) Also what shall be the reason for LR and IP to be contain same address at a time causing undesired looping with in this undesired function.Peter Vlna