Hi,
I have questions about function of IPUx_DI10_STAT register of IPU in i.MX6DQ reference manual.
1. There are status bits of DI0_CNTR_FIFO_FULL and DI0_READ_CNTR_EMPTY.
What FIFO status does it indicate? Does this FIFO use data transfer from DMFC/Memory to DI0?
2. There are status bits of DI0_READ_FIFO_FULL and DI0_READ_FIFO_EMPTY.
What FIFO status does it indicate? Does this FIFO use data transfer from smart Display or DMFC/Frame buffer?
Best Regards,
Sugiyama
Hi Sugiyama
>Does it means DI0_CNTR_FIFO is for output data to parallel display?
yes
Best regards
igor
Hi Sugiyama
>1. There are status bits of DI0_CNTR_FIFO_FULL and DI0_READ_CNTR_EMPTY.
> What FIFO status does it indicate?
This FIFO is part of the DI0 synchronizer, depicted on Figure 37-39 DI's block diagram
i.MX6DQ Reference Manual
http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf
>Does this FIFO use data transfer from DMFC/Memory to DI0?
No. DMFC has not direct connection to DI0, as shown on p.33 "IPUv3H – Internal Structure"
presentation on
https://community.nxp.com/docs/DOC-100482
>2. There are status bits of DI0_READ_FIFO_FULL and DI0_READ_FIFO_EMPTY.
> What FIFO status does it indicate?
This FIFO is part of the DI0 synchronizer, depicted on Figure 37-39 DI's block diagram.
>Does this FIFO use data transfer from smart Display or DMFC/Frame buffer?
It i used for smart display, not supported in i.MX6 IPU.
Best regards
igor
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Hi, Igor,
Thank you for the answer.
There are two synchronizer in Fig 37-39.
Does DI0_CNTR_FIFO_ refer to DC's Data Accumulater and clock domain Synchronizer?
If so, is it possible that this FIFO status detect data error sent from DC?
Does DI0_READ_FIFO refer to Parallel Interface Data Synchronizer?
Best Regards,
Sugiyama
Hi Sugiyama
>There are two synchronizer in Fig 37-39.
>Does DI0_CNTR_FIFO_ refer to DC's Data Accumulater and clock domain Synchronizer?
it refers to Parallel Interface Data Synchronizer
>Does DI0_READ_FIFO refer to Parallel Interface Data Synchronizer?
yes
Best regards
igor
Hi, Igor,
Thank you for the answer.
Does it means DI0_CNTR_FIFO is for output data to parallel display?
Best Regards,
Sugiyama