In the next sections we are going to discuss one by one in details each of these topics. Even if the focus of the article is on S32K14x product family, most of the information provided is generic and applicable to any other digital control system the main difference being the actual Simulink implementation.
|Fig. 1: Application Mapping - HW & SW modules used for Phase Currents measurement are highlighted in green|
|Current Sensing Method||Construction||Advantages||Disadvantages|
Provides good accuracy;
High power dissipation;
Not suitable for high current applications;
Small or no-cost can be implemented directly on PCB tracks;
Poor accuracy due temperature variations;
Need to be precisely calculated from beginning for proper balance between accuracy and power dissipation;
Hall effect sensor
Provides galvanic isolation;
Low power dissipation;
Needs additional electronic components;
Provides galvanic isolation;
High current sensing capabilities;
Large size & mass;
Works only in AC;
Requires special hardware to avoid magnetic saturation;
Magnetic field susceptibility;
|Current Measurement Strategy||Sensor Type||Advantages||Disadvantages|
Inverter current sensing shunts
Less power dissipation since the current is not passing all the time thru it;
Good balance between cost and PCB area;
Need 3 shunts resistors, one for each phase;
Need to synchronize the readings with the times when lower switches are in conduction
EMI noise due to proximity of inverter switches
DC-link current sensing shunt
Single shunt needed;
Small area footprint;
Large power dissipation capabilities
Not suitable for high current applications
Need complex SW to reconstruct the 3 phase currents
Motor phases current sensing shunts
Simplifies SW measuring routines since the current flow is continuously thru the shunt
Can be swapped easily for supporting various current ranges
Very high power dissipation
Additional PCB components needed to interface the sensors with the MCU logic
As general assumption, the current that flows into the motor windings (as depicted in Fig. 5 by the current in phase A) will be considered as a positive current. Currents that flows out of the motor windings are considered to be negative current.
|Fig. 7: Voltage drop across a shunt resistor placed in lower part of inverter leg in case of the positive current passing thru|
Based on Fig. 10 system topology we can identify up to seven (yes! 7) sources of delays that add together and having a negative impact on the measurements. In the next table is shown the source of the delay, the overall impact and the typical numbers you should expect when dealing with such system topology as the one from MotorGD DevKit.
Lets take it one by one and see how those delays influence the current measurements:
- PWM Dead time (DT) insertion. This is mostly given by the hardware design restrictions that needs to consider the type of load and the transistors used to switch the phase voltages. Since the transistors needs some time to enter or exit the conduction state, the SW must ensure there is no situation when both upper and lower transistors are in conduction at the same moment. A typical value for DT might be between 100ns up to 2us depending on various factors in the system. As shown in Fig. 11, after adding the dead time for on the desired PWM waveform, what we get is shift to the right for both PWM mid point and the rising edges. Therefore, immediately after finishing computing the proper PWM via Space Vector Modulation technique, we start to see the first delay.
- Between the moment when the PWM signal is computed and available inside the MCU FTM peripheral and the moment it reaches the actual MOSFET gate, there is an additional delaying chain cause by the signal response of various opto-couples and pre-drivers that are used to condition the signal and separates the high voltage side from low voltage one. This additional delay is shown in Fig. 12 and represent another shifting to the right of the PWM commands compared with the moment when FTM internal counter was initialized.
- At this point in time the PWM command that controls the MOSFET transistor are available but all transistors have a time ON and OFF due to their intrinsic characteristics. Depending on the class of transistors you may have and the voltage level you need to switch ON/OFF, this delay may be shortef and longer. In Fig. 13, is show the entire delay (Delay2) between the theoretical switching point (marked here by the compare level CMP2) and the moment when the actual terminal voltage is switched.
- Finally we reach to the point when the transistors are in conduction and the current have a path to flow thru the shunt resistor. In Fig. 14 is depicted the moment in time when the current start to flow. At this point you can see the delay between what has been commanded as what has been actually obtained as current flow thru motor winding.
|Fig. 14: Delay between desired PWM command and the moment when current flows thru the shunt resistor|
- The last chain of delay that influence the current measurements is made of the low pass filter (LPF) shown in Fig. 10 and the amplifier slew rate as depicted in Fig. 15. As can be seen marked with a green circle the moment when the ADC can safety acquire the shunt voltage drop due to current passing thru is far to right delayed compared to the original desired PWM mid point.
Understanding and knowing all these factors will allow us to successfully read the correct values of the motor phase currents. As you can see, it is up to the software side to compensate for all these delays and perform the actual FOC accordingly.
At this point you may ask yourself why not reading the phase C current directly since there is a shunt already available for that purpose. That is a legitimate question but due to the hardware constrains we are not going to use that third shunt and let me explain why.
As it has been explained the delays may have an big impact on the current measurements and this effect is even more important at high speed when we need to which the PWM faster. Spinning the motor faster it means we have to supply the motor with higher voltage that can only be achieved by maintaining the upper switches in conduction for longer time periods. In Fig. 6 was explained that we need a critical time interval to keep the lower transistor ON.
Therefore, considering the importance of reading the currents as closed as possible in the middle of the PWM lower switch command we would like to avoid doing multiple ADC sampling in that short time interval. The S32K144 MCU has two ADC modules and we can route the signals from both shunts to each of the ADC in order to sample in parallel the phase A and phase B currents. Any other combination will lead to an additional delay in measuring the phase C current and Kirchhoff law is going to be violated since the sampling is done to different moments in time.
Expect for the phase currents that needs to be sampled in the same time, nothing prevent us for measuring additional analogue values that does not need to be synchronized with the PWM waveform. As it shown in Fig. 17, we are going to read two additional signals that will helps us with motor and drive protection in the future. These two additional signals represent the DC-link voltage and current.
This signal are routed to the S32K144 MCU via dedicated pins that reach the ADC converters as shown in Fig. 18.
By default the correspondence between the signals and the ADC instances is shown in the table below. Note that the phase currents are routed by default to the same ADC0 converter. If we leave them like this is going to complicate the application since we will have to deal with an additional delay between the sampling moment of phase A current and the moment when we sample again to read the phase B current. In this time interval the current thru phase B might change the value and the FOC may be distorted.
To solve these kind of issues, the S32K14x product families allows you to perform ADC hardware channels interleaving as shown in Fig. 19. In the hardware interleaved mode, a signal on the pin PTB1 can be sampled by both ADC0 and ADC1 in the same time. The interleaved mode is enabled by SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits.
Using this hardware trick we are going to re-route the phase B current measurement to the ADC1 instead of ADC0 and the new analogue pin assignment will look like this:
The last unknown piece of the puzzle is how synchronize the ADC measurement with the PWM command. Once again the S32K14x product family comes in handy with a rich feature set. The MCU contains a dedicated module for inter-connectivity of various hardware modules. This module is called TRGMUX and provides an extremely flexible mechanism for connecting various trigger sources to multiple pins/peripherals as shown in Fig. 20.
To trigger the ADC conversion we are going to use the FTM initialization trigger (INIT_TRIG) functionality. The INIT_TRIG is going to raise an event each time the PWM counter is re-initialized signaling this way the beginning of a new PWM period. This way the TRGMUX can re-route this event to the ADC modules to signal the moment when the ADC should start the acquisitions.
As we have found out from Dual-Shunt Sensing Technique section, apart of PWM to ADC synchronization we also need to handle various sources of delays in the system. The S32K14x MCU families have a dedicated peripheral called Programmable Delay Block (PDB) that can trigger specific events based on a pre-condition.
In our case, we are going to configure the PDB instances to receive the same FTM INIT_TRIG event and to command the ADC acquisition at a specific moment in time which is delayed compared to the beginning of the PWM period. The specific delay timing intervals will be discussed in the next section.
The overall ADC triggering concept can be summarize in Fig. 22. The FTM issue the counter initialization trigger which is used as a trigger input of the PDB. The PDB is then used to trigger the ADC. Each ADC channel in the PDB module supports up to 8 pre-triggers, which could be used as the ADC hardware channel selection to precondition the ADC block prior to an actual trigger. After a pre-trigger, the ADC trigger initiates the ADC conversion. When a PDB pre-trigger starts an ADC conversion, an internal lock associated with the corresponding pre-trigger is activated. This lock becomes inactive when receiving the conversion complete (COCO) signal from the ADC.
As can be seen from Fig. 22 the main CPU is not involved in this mechanism once the entire chain of events is configured. This leaves more resources available for the programmer to implement the application.
The Simulink blocks that are going to be added in this module are highlighted in Fig 23, in red while the blocks that are going to contain small modifications relative to the previous module are marked with magenta.
The Simulink model can be broken apart in various configuration steps as shown below.
MOSFET Pre-Driver Configuration
The first thing we have to do is to make sure MOSFET pre-driver is configured correctly according with MC34GD3000 datasheet. To do configure it correctly we need to perform a specific sequence of commands in order to make sure pre-driver outputs are enabled and latched prior to normal operation:
- RST input signal goes HIGH while the EN1 and EN2 input signals remain LOW;
EN1 and EN2 inputs are set to HIGH state
PA_LS_G, PB_LS_G, and PC_LS_G outputs are toggled HIGH for about 1.0 μs (HS outputs are enabled, but not latched)
Toggle PA_HS_G, PB_HS_G, and PC_HS_G outputs LOW for dead-time periord plus at least 0.1 μs
Fig. 24: MOSFET pre-driver configuration (a) - left side shows the pre-driver signals (b) - right shows the full initialization sequence
The entire initialization sequence is implemented in Simulink using the State-Flow charts and triggered subsystems that mimics the sequence shown in Fig. 24b. The subsystem is implemented in the Fast Loop Control and it is executed only once after reset.
The SPI communication is not yet implemented since it is not in the purpose of this module. All the data are prepared and will be sent to the pre-driver in a future module when we will have to configure various hardware protections.
The Flex Timer Module needs to be configured to:
- perform a special PWM start-up sequence to enable the pre-driver configuration;
- send an interrupt each time the timer is getting reinitialized in order to allow PWM-PDB-ADC syncronization
Since we have to perform a special pre-driver configuration we need to make sure we have a full control over the moments when the PWM are activated. At initialization phase we are going to deactivate the PWM signal generation from "Start pin generation immediately after initialization" option and disabling "Initialization Trigger"
These two options will be enabled in the Control_Logic/enable_pwm subsystem shown in Fig. 25, where we have used an interesting combination of NXP Toolbox library blocks and Simulink Coder Custom Code blocks to call the FTM function that enables the trigger generation, as it is shown in Fig. 27.
|Fig. 27: (a) pwm_enable subsystem, (b) FTM_PWM_Disable_Enable block configuration, (c) Simulink Coder Custom Code Block to call the function that setup the FTM initialization trigger|
First step in configuration of the ADC modules ADC0 and ADC1 is to configure the SIM module to interleave the ADC channels in order to allow us to read the phase current A and B in parallel on both ADC modules in the same time. Since there is no dedicated Simulink block for this we will have to write a custom piece of code that can be executed during system initialization phase. This is an easy task using the Simulink Coder dedicated blocks.
Using a Model Header Simulink Coder block we are going to write a generic function that could be reused to setup the SIM module that handles the ADC hardware channel interleaving. This piece of code is going to be place in the beginning of the C-file that is automatically generated by Simulink for our model.
All that remains now is to call this function at the initialization stage with the proper arguments that configures the PTB1 input to be sampled by the ADC1 on AD15 input channel.
The initialization for both ADC modules ADC0 and ADC1 is identical. The main parameters that needs to be configured are shown in Fig. 30. For more details of each one please consult the Help. As shown here, the ADC are configured to use the highest resolution possible and to have the conversions automatically started based on hardware event controlled by the PDB peripheral
The final ADC configuration that needs to be done is to setup the conversion channels associated with the values we want to measure. The ADC conversion results are currently read in the PDB interrupt handle which is synchronized with the FTM PWM initialization trigger.
The second part of this article can be found here: Module 6: Current Sensing (Part 2/2)