Module 6: Current Sensing (Part 1/2)

Discussion created by dumitru-daniel.popa Employee on Feb 5, 2018
Latest reply on Mar 26, 2018 by dumitru-daniel.popa






In this module of the 3-Phase PMSM Control Workshop with NXP's Model-Based Design Toolbox , we are going to implement and test the most critical part of the digital control system: motor phase current measurements. As we have discussed in Module 2: PMSM and FOC Theory  the quintessence of Field Oriented Control (FOC) is to align the stator current vector with the PMSM rotor Q-axis and the way we can reach that goal is by measuring the actual PMSM phase currents.


Current sensing and measuring are one the most complex task you may have to deal with in the motor control applications since it involve both hardware and software resources. Understanding the hardware that sense the currents and then being able to measure accurately the current values require you to have a good understanding about: 

  • How the current sensor works and hardware topology
  • Delays propagation and their influence on actual measurements
  • Synchronization between PWM commands and ADC conversions
  • Specialized custom hardware features design to improve the overall measurement
  • Hardware interrupts and trigger events
  • Software data processing and parameters calculation 


In the next sections we are going to discuss one by one in details each of these topics. Even if the focus of the article is on S32K14x product family, most of the information provided is generic and applicable to any other digital control system the main difference being the actual Simulink implementation.


In Fig. 1, which represent the global application mapping diagram as discussed in Module 3: System Partitioning , are shown the main hardware blocks that are going to be configured for PMSM phase currents measurement. We are going to reuse the model developed in Module 5: V/F Scalar Control  which will allow us to test the measurement technique in dynamic regime. The interactions between host PC and hardware will be done via OpenSDA serial communication that will be used to download the code generated from MATLAB and to visualize various control signals with FreeMASTER. 

Fig. 1: Application Mapping -  HW & SW modules used for Phase Currents measurement are highlighted in green







As designers or engineers in the field of power electronics, power supplies, battery management systems, motor drives and many other areas one of the most common faced problem is the need to measure currents accurately. In general the current needs to be measured for fault protection or functional control. For this application we need to measure the current for three main reasons:

  • Functional - motor control feedback for FOC in order to orient the stator current vector
  • Protection - against over-current and short circuit
  • Information - about power consumption levels 


In practice, there are four major current sensing methods commonly available. These methods are shown in table below, together with the advantages and disadvantages of each.


Current Sensing MethodConstructionAdvantagesDisadvantages



Shunt Resistor


Low cost;

Provides good accuracy;

Wide-band measurements;


High power dissipation;

Not suitable for high current applications;





Small or no-cost can be implemented directly on PCB tracks;

Reduce BOM;

Poor accuracy due temperature variations;

Need to be precisely calculated from beginning for proper balance between accuracy and power dissipation;


Hall effect sensor


Provides galvanic isolation;

Low power dissipation;

High cost;

Limited bandwidth;

Needs additional electronic components;



Current transformer


Provides galvanic isolation;

High current sensing capabilities;

Large size & mass;

Works only in AC;

Requires special hardware to avoid magnetic saturation;

Magnetic field susceptibility;


Based on the advantages of low cost and accurate wide-band measurement the precision shunt resistors, are frequently the best answer for most of the applications.  In this case, choosing the best resistance R value is a question of balance between accuracy vs. power dissipation.

Shunt resistors works on a simple principle of Ohm Law: I = U/R. If the resistance R it is too high then power (P = I^2*R) will be wasted, excess heat  will be generated and the voltage regulation is lost due to change in R value. Consequently, if R is too low then the sense voltage will be correspondingly low, so issues with noise and resolution will limit the accurate measurement of current.


Another important aspect to consider when dealing with shunt resistors is the parasitic inductances that can cause wrong results. Any shunt resistor contains an inductance component that creates a voltage spike as shown in Fig. 2. 



Fig. 2: Shunt parasitic inductance effect


To reduce or eliminate the effect of parasitic inductances, special resistors and PCB layouts are used. The PCB track design around current shunt resistors is critical for obtaining an accurate current sensing. The main difference between dealing with a shunt resistor and a normal resistor is that four rather than two tracks must be provided to form a Kelvin connection, even where the component itself has only two terminals. These 2 additional tracks (V1-V2) that forms the Kelvin connection as shown in Fig. 3 are actually used for measuring the voltage drop across the shunt resistor, which is proportional with the current that needs to be measured.


The scope is to minimize the conductive path shared between the current path and the sensing loop, which would increase the tolerance on temperature variation and reduce the effect of parasitic inductance. 

Fig. 3: PCB design used to sense the currents via shunt resistors







Once the current sensing method is selected, the next step is to define how and where we are going to use the shunt resistors to acquire the information about the current. In motor control applications there are three main strategies that can be employed to accurately measure motor phase currents and the main difference between them is the relative position of the current sensors:


Current Measurement StrategySensor TypeAdvantagesDisadvantages



Inverter current sensing shunts

(Dual-Shunt technique)


Less power dissipation since the current is not passing all the time thru it;

Small shunt;

Good balance between cost and PCB area;

Need 3 shunts resistors, one for each phase;

Need to synchronize the readings with the times when lower switches are in conduction

EMI noise due to proximity of inverter switches 

DC-link current sensing shunt

(Single-Shunt technique)



Single shunt needed;

Small area footprint;

BOM optimal

Large power dissipation capabilities

Not suitable for high current applications

Need complex SW to reconstruct the 3 phase currents



Motor phases current sensing shunts


Simplifies SW measuring routines since the current flow is continuously thru the shunt 

Can be swapped easily for supporting various current ranges

Very high power dissipation

Large volume

Additional PCB components needed to interface the sensors with the MCU logic


The MotorGD DevKit comes equipped by default with all that is needed to address the first two use-cases as highlighted in Fig. 4:

  • Three inverter current sensing shunts, one for each inverter phase. Since in most of the cases the PMSM forms a 3-phase symmetric isolated system instead of sampling all three shunts resistors, you can use only 2 out of 3 to implement the standard PMSM phase current measurements which is also known as Dual-Shunt method. The third current can be easily computed in SW since Kirchhoff circuit law states that the sum off all 3 currents is null (Ia + Ib + Ic  = 0)
  • One DC-link current sensing shunt that will be mainly used for current protection and power consumption monitoring. The current sensing information from this DC-link shunt can be used for what is called Single-Shunt method. 
Fig. 4: MotorGD DevKit Current measurement shunt resistors configuration







Dual-Shunt sensing techniques is one of the most common used method to measure the phase currents in motor control applications. This method have a good balance between advantages and disadvantages being suitable to be implemented in most of the applications. As depicted in Fig. 5, we are going to use the phase A and phase B inverter shunts to measure the voltage drop across the shunt resistor.


As it is depicted here and as mentioned before, the currents can be measured only when the lower switches are in conduction. Please notice i'm using the general naming convention as switch that incorporates a transistor and a anti-parallel diode. Depending on the load type and the commutation sequence the current may pass thru transistor or diode (for details about this please check: Module 4: Space Vector Modulation )

Fig. 5: Dual-shunt current measurement topology 


As general assumption, the current that flows into the motor windings (as depicted in Fig. 5 by the current in phase A) will be considered as a positive current. Currents that flows out of the motor windings are considered to be negative current.    


Since the shunt is placed in the lower part of the inverter, the voltage potential read from the shunt terminals is negative when the current flows into the motor winding. Therefore this need to be taken into consideration in SW when we are going to read the values from ADC. A negative voltage on the shunt resistor indicates a positive current thru the motor winding.


Another important aspect of dual-shunt measurement technique is PWM critical pulse width consideration. Since the ADC acquisition of the shunt voltage drop is done when the lower switch is activated, we need to maintain a minimal PWM command for that transistor in order to measure a relevant information.


This critical pulse width as depicted in Fig. 6, is needed for three main reasons:

  • Voltage drop stabilization due to load inductance nature of motors. The effect of load inductance can be optimized but it can not be fully eliminated;
  • System propagation delays between SW and HW components involved in the process. The delays form a chain that can be reduced by selecting components with fast response time but it can not be fully eliminated;
  • ADC sampling and acquisition time can be optimized at design phase but never fully eliminated;


Fig. 6: PWM critical pulse width in case of dual-shunt current measurement  


For a better understanding off all the variables we need to take into consideration lets us have a look at a typical shunt resistor voltage drop in case of a positive current passing thru. For readability, please consider the case of the phase A current measurement as depicted in Fig. 5.


As it shown in this Fig. 7,oscilloscope capture using the MotorGD DevKit, with cyan we have the 10kHz PWM signal command that controls the lower inverter switch on phase A, while the yellow signal represents the voltage drop on the inverter phase A shunt resistor. When there is no current flowing thru the value of the drop voltage is zero. When the current flows thru the MOSFET the voltage drop as a stable value, while by the time the current flows thru the anti-parallel diode the voltage is slowly going down to zero.

For more details regarding the current flows thru transistor or diode please check the training video in Module 4: Space Vector Modulation 


Fig. 7: Voltage drop across a shunt resistor placed in lower part of inverter leg in case of the positive current passing thru


If we zoom in a little bit we will see the effect of voltage drop stabilization time and why we need that delay when performing the current measurements. Any measurement in that region is prone to error due to current oscillations due inductance nature of the load. We have to wait until the current reaches a steady state regime thru the load and shunt before standing the ADC sampling and acquisition. 


Fig. 8: Zoom in detail with shunt voltage drop stabilization.


As it is shown in Fig. 7, in order to read the current you need to know then the lower switch is in conduction and more specifically when the current flows thru the MOSFET. Bottom line for an accurate current measurement, the ADC sampling must be synchronized with the PWM commands. To better understand this concept lets consider a simple inductor as load and lets assume we want to regulate the current thru such a load.


Fig. 9 shows the two possible scenarios that can be used for current measurement in this case and the effect of these tow scenario over the quantities acquired:

  • In asynchronous sampling scenario, there is no correlation between the PWM signal (cyan waveform) and the ADC trigger (green waveform). The ADC conversion may happen to random time intervals as depicted in the upper case. Assuming the PWM duty factor is constant and the real current thru load varies in a saw-tooth waveform pattern, then the measured current will be wrong showing various levels depending on the moment the ADC was triggered.
  • in the synchronized sampling scenario, the ADC conversion is triggered always in the middle of the PWM ON period. This mechanism will ensure that all the time we read the actual current thru the inductor in the same moment. The dark-red waveform shows that using this method we can read a steady average current all the time.  


Fig. 9: Asynchronous vs. Synchronous current measurement ADC sampling


The last topic we have to discuss before implementing the actual application is the system delays that may affect the current measurements. Now that we know that we need to synchronize the PWM pulse generation with the ADC sampling we need to understand how various transformation between the moment when we compute the next PWM duty cycle until the moment we perform the measuring will affect the system. A typical processing chain is depicted in Fig. 10.


Fig. 10: Processing chain between the MCU computation and actual current measurements


Based on Fig. 10 system topology we can identify up to seven (yes! 7) sources of delays that add together and having a negative impact on the measurements. In the next table is shown the source of the delay, the overall impact and the typical numbers you should expect when dealing with such system topology as the one from MotorGD DevKit.



Lets take it one by one and see how those delays influence the current measurements:

  • PWM Dead time (DT) insertion. This is mostly given by the hardware design restrictions that needs to consider the type of load and the transistors used to switch the phase voltages. Since the transistors needs some time to enter or exit the conduction state, the SW must ensure there is no situation when both upper and lower transistors are in conduction at the same moment. A typical value for DT might be between 100ns up to 2us depending on various factors in the system. As shown in Fig. 11, after adding the dead time for on the desired PWM waveform, what we get is shift to the right for both PWM mid point and the rising edges. Therefore, immediately after finishing computing the proper PWM via Space Vector Modulation technique, we start to see the first delay.
Fig. 11: Delay due to Dead Time (DT) insertion
  • Between the moment when the PWM signal is computed and available inside the MCU FTM peripheral and the moment it reaches the actual MOSFET gate, there is an additional delaying chain cause by the signal response of various opto-couples and pre-drivers that are used to condition the signal and separates the high voltage side from low voltage one. This additional delay is shown in Fig. 12 and represent another shifting to the right of the PWM commands compared with the moment when FTM internal counter was initialized.
Fig. 12: Delay due to opto-coupler and pre-drivers
  • At this point in time the PWM command that controls the MOSFET transistor are available but all transistors have a time ON and OFF due to their intrinsic characteristics. Depending on the class of transistors you may have and the voltage level you need to switch ON/OFF, this delay may be shortef and longer. In Fig. 13, is show the entire delay (Delay2) between the theoretical switching point (marked here by the compare level CMP2) and the moment when the actual terminal voltage is switched.
Fig. 13: Delay due to transistors entering/exiting the conduction
  • Finally we reach to the point when the transistors are in conduction and the current have a path to flow thru the shunt resistor. In Fig. 14 is depicted the moment in time when the current start to flow. At this point you can see the delay between what has been commanded as what has been actually obtained as current flow thru motor winding.
Fig. 14: Delay between desired PWM command and the moment when current flows thru the shunt resistor
  • The last chain of delay that influence the current measurements is made of the low pass filter (LPF) shown in Fig. 10 and the amplifier slew rate as depicted in Fig. 15. As can be seen marked with a green circle the moment when the ADC can safety acquire the shunt voltage drop due to current passing thru is far to right delayed compared to the original desired PWM mid point.  
Fig. 15: Delays due to filtering and amplifier slew rate


Understanding and knowing all these factors will allow us to successfully read the correct values of the motor phase currents. As you can see, it is up to the software side to compensate for all these delays and perform the actual FOC accordingly.






Now that we know what we have to do in order to read the currents, lets see that MotorGD DevKit is offerings and how can we use the signals to convert the information from analogue to digital. As shown in Fig. 16, we are going to use the inverter phase A and B shunts to capture the value of motor phase A and phase B. Based on these 2 values we are going to compute the third current on phase C.


Fig. 16: MotorGD DevKit 3-phase inverter schematic


At this point you may ask yourself why not reading the phase C current directly since there is a shunt already available for that purpose. That is a legitimate question but due to the hardware constrains we are not going to use that third shunt and let me explain why.


As it has been explained the delays may have an big impact on the current measurements and this effect is even more important at high speed when we need to which the PWM faster. Spinning the motor faster it means we have to supply the motor with higher voltage that can only be achieved by maintaining the upper switches in conduction for longer time periods. In Fig. 6 was explained that we need a critical time interval to keep the lower transistor ON.


Therefore, considering the importance of reading the currents as closed as possible in the middle of the PWM lower switch command we would like to avoid doing multiple ADC sampling in that short time interval. The S32K144 MCU has two ADC modules and we can route the signals from both shunts to each of the ADC in order to sample in parallel the phase A and phase B currents. Any other combination will lead to an additional delay in measuring the phase C current and Kirchhoff law is going to be violated since the sampling is done to different moments in time. 


Expect for the phase currents that needs to be sampled in the same time, nothing prevent us for measuring additional analogue values that does not need to be synchronized with the PWM waveform. As it shown in Fig. 17, we are going to read two additional signals that will helps us with motor and drive protection in the future. These two additional signals represent the DC-link voltage and current.


Fig. 17: Analogue values to be read from MotorGD DevKit


This signal are routed to the S32K144 MCU via dedicated pins that reach the ADC converters as shown in Fig. 18.

Fig. 18: S32K144 analogue signal routing


By default the correspondence between the signals and the ADC instances is shown in the table below. Note that the phase currents are routed by default to the same ADC0 converter. If we leave them like this is going to complicate the application since we will have to deal with an additional delay between the sampling moment of phase A current and the moment when we sample again to read the phase B current. In this time interval the current thru phase B might change the value and the FOC may be distorted.


To solve these kind of issues, the S32K14x product families allows you to perform ADC hardware channels interleaving as shown in Fig. 19. In the hardware interleaved mode, a signal on the pin PTB1 can be sampled by both ADC0 and ADC1 in the same time. The interleaved mode is enabled by SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits.

Fig. 19: S32K14x ADC hardware interleaved channels


Using this hardware trick we are going to re-route the phase B current measurement to the ADC1 instead of ADC0 and the new analogue pin assignment will look like this:


The last unknown piece of the puzzle is how synchronize the ADC measurement with the PWM command. Once again the S32K14x product family comes in handy with a rich feature set. The MCU contains a dedicated module for inter-connectivity of various hardware modules. This module is called TRGMUX and provides an extremely flexible mechanism for connecting various trigger sources to multiple pins/peripherals as shown in Fig. 20.


To trigger the ADC conversion we are going to use the FTM initialization trigger (INIT_TRIG) functionality. The INIT_TRIG is going to raise an event each time the PWM counter is re-initialized signaling this way the beginning of a new PWM period. This way the TRGMUX can re-route this event to the ADC modules to signal the moment when the ADC should start the acquisitions.

Fig. 20: PWM - ADC synchronization


As we have found out from Dual-Shunt Sensing Technique section, apart of PWM to ADC synchronization we also need to handle various sources of delays in the system. The S32K14x MCU families have a dedicated peripheral called Programmable Delay Block (PDB) that can trigger specific events based on a pre-condition. 

In our case, we are going to configure the PDB instances to receive the same FTM INIT_TRIG event and to command the ADC acquisition at a specific moment in time which is delayed compared to the beginning of the PWM period. The specific delay timing intervals will be discussed in the next section.


Fig. 21: PDB triggering scheme of ADC conversion using same event synchronization source INIT_TRG


The overall ADC triggering concept can be summarize in Fig. 22. The FTM issue the counter initialization trigger which is used as a trigger input of the PDB. The PDB is then used to trigger the ADC. Each ADC channel in the PDB module supports up to 8 pre-triggers, which could be used as the ADC hardware channel selection to precondition the ADC block prior to an actual trigger. After a pre-trigger, the ADC trigger initiates the ADC conversion. When a PDB pre-trigger starts an ADC conversion, an internal lock associated with the corresponding pre-trigger is activated. This lock becomes inactive when receiving the conversion complete (COCO) signal from the ADC.


Fig. 22: ADC trigger concept that implements the PWM-ADC synchronization

As can be seen from Fig. 22 the main CPU is not involved in this mechanism once the entire chain of events is configured. This leaves more resources available for the programmer to implement the application.







As mentioned in the Introduction, we are going to reuse and enhance the model developed in the previous module Module 5: V/F Scalar Control to perform:

  • Hardware configuration for a proper current sensing using PWM-PDB-ADC synchronization
  • Software computation for scaling the ADC conversion into the real values for currents and voltages


The Simulink blocks that are going to be added in this module are highlighted in Fig 23, in red while the blocks that are going to contain small modifications relative to the previous module are marked with magenta.

Fig. 23: Top level Simulink model used for ADC measurements 


The Simulink model can be broken apart in various configuration steps as shown below.


MOSFET Pre-Driver Configuration

The first thing we have to do is to make sure MOSFET pre-driver is configured correctly according with MC34GD3000 datasheet. To do configure it correctly we need to perform a specific sequence of commands in order to make sure pre-driver outputs are enabled and latched prior to normal operation:

  • RST input signal goes HIGH while the EN1 and EN2 input signals remain LOW;
  • EN1 and EN2 inputs are set to HIGH state

  • PA_LS_G, PB_LS_G, and PC_LS_G outputs are toggled HIGH for about 1.0 μs (HS outputs are enabled, but not latched)

  • Toggle PA_HS_G, PB_HS_G, and PC_HS_G outputs LOW for dead-time periord plus at least 0.1 μs

Fig. 24: MOSFET pre-driver configuration (a) - left side shows the pre-driver signals (b) - right shows the full initialization sequence


The entire initialization sequence is implemented in Simulink using the State-Flow charts and triggered subsystems that mimics the sequence shown in Fig. 24b. The subsystem is implemented in the Fast Loop Control and it is executed only once after reset. 

Fig. 25: Pre-driver initialization Simulink model

The SPI communication is not yet implemented since it is not in the purpose of this module. All the data are prepared and will be sent to the pre-driver in a future module when we will have to configure various hardware protections.



FTM Configuration

The Flex Timer Module needs to be configured to:

  • perform a special PWM start-up sequence to enable the pre-driver configuration;
  • send an interrupt each time the timer is getting reinitialized in order to allow PWM-PDB-ADC syncronization


Since we have to perform a special pre-driver configuration we need to make sure we have a full control over the moments when the PWM are activated. At initialization phase we are going to deactivate the PWM signal generation from "Start pin generation immediately after initialization" option and disabling "Initialization Trigger"

Fig. 26: FTM_Three_Phase_Output Simulink block settings


These two options will be enabled in the Control_Logic/enable_pwm subsystem shown in Fig. 25, where we have used an interesting combination of NXP Toolbox library blocks and Simulink Coder Custom Code blocks to call the FTM function that enables the trigger generation, as it is shown in Fig. 27.












Fig. 27: (a) pwm_enable subsystem, (b) FTM_PWM_Disable_Enable block configuration, (c) Simulink Coder Custom Code Block to call the function that setup the FTM initialization trigger


ADC Configuration

First step in configuration of the ADC modules ADC0 and ADC1 is to configure the SIM module to interleave the ADC channels in order to allow us to read the phase current A and B in parallel on both ADC modules in the same time. Since there is no dedicated Simulink block for this we will have to write a custom piece of code that can be executed during system initialization phase. This is an easy task using the Simulink Coder dedicated blocks. 


Using a Model Header Simulink Coder block we are going to write a generic function that could be reused to setup the SIM module that handles the ADC hardware channel interleaving. This piece of code is going to be place in the beginning of the C-file that is automatically generated by Simulink for our model. 

Fig. 28: SIM model interleave function body


All that remains now is to call this function at the initialization stage with the proper arguments that configures the PTB1 input to be sampled by the ADC1 on AD15 input channel. 

Fig. 29: ADC interleave selection for PTB1 input


The initialization for both ADC modules ADC0 and ADC1 is identical. The main parameters that needs to be configured are shown in Fig. 30. For more details of each one please consult the Help. As shown here, the ADC are configured to use the highest resolution possible and to have the conversions automatically started based on hardware event controlled by the PDB peripheral

Fig. 30: ADC instances configuration


The final ADC configuration that needs to be done is to setup the conversion channels associated with the values we want to measure. The ADC conversion results are currently read in the PDB interrupt handle which is synchronized with the FTM PWM initialization trigger. 

Fig. 31: Simulink model for ADC conversion results reading


The second part of this article can be found here: Module 6: Current Sensing (Part 2/2)