For our IMX6Q based custom board, we are using Alliance 4x 4Gbit memory chips. However the maximum DDR3 frequency of the chip is said to be 800MHz (DDR3-1600). When I run OpenGL applications, few boards just randomly hang. I am using boundary devices u-boot-v-2016 and kernel 4.1.15_0.2 !
1. So according to the speed grade this should be only compatible with IMX6Q 400MHz (the other option being 528MHz) DDR operation right ?
2. I performed the memory calibration for 400MHz DDR frequency and updated relevant DCD headers in u-boot source files (800mhz_4x256mx16_our.cfg).
3. However when I login and check the clock_summary in kernel, the mmdc_ch0_axi, mmdc_ch1_axi as well as gpu3d_core_sel clock roots are still seen to be 528MHz. Please refer following link for the summary.
4. So if the u-boot ddr timing is set for 400MHz, shouldn't those memory control clock roots be set to 400MHz (or 396MHz) as well ? In that case which source file should be changed in the kernel ? I can see that CCM_CBCMR is the relevant register for the clock roots ! i.e. it's set to something else in arch/arm/mach-imx/ddr3_freq_imx6.S in multiple times.
Thanks in Advance