I have configured flexio to implement an spi peripheral that lights off 10 x (2 byte) spi transactions on every falling edge of a pin without any CPU intervention. I have two shift registers, one in receive mode and one in transmit mode. The transmit shift register is loaded using a 20 byte DMA circular buffer, and the receive shift register is read into a larger circular buffer using DMA. My goal is to have the mcu sit in VLPW mode while accumulating data from an external sensor. It works correctly in RUN mode however when I enter VLPW, the DMA can no longer keep up unless I lower the clock frequency of the spi. (I am getting TX underruns)
From what I understand, the max DMA requests per second is SystemClock / 11.5.
In VLPR mode, the SystemClock is 4MHz.
So I thought that I should be able to get 4Mhz / 11.5 DMA requests/second.
Since each DMA request loads the shift register with 1 byte, I thought I should get (4/11.5*8) 2.78Mbit/s.
In reality, I could only achieve 0.75Mbit/s.
I am guessing this is somehow related having two DMA channels accessing the same slave(flexio shift regs), but I couldn't find any documentation about how this affects performance. I am using round robin arbitration so wouldn't make sense if the bandwidth was split evenly between the two channels, so 2.78/2=1.4Mbit/s? I don't understand why it would only be 0.75Mbits/s.
Any thoughts on how to speed up DMA requests without leaving vlpw?