A few months ago we had our custom i.MX6 Dual board sent to a lab for the CISPR 25 test to measure both radiated and conducted emissions. We failed the test due to the pixel clock on the LVDS lines. When the pixel clock was set at 52MHz, we failed both the peak and average limits around 310MHz (other frequencies failed as well). See image below.
When we changed the pixel clock to 48MHz, you can see the spike shift to 290MHz, which makes it under the limit for this frequency. However, there are other areas that we are still over the average limit.
We have added shielding around the flex cable going to the LCD, common mode chokes and ferrite beads to the LVDS pairs hoping this will reduce the emissions, but in talking to the test engineer, he said that sometimes customers can fix this by making the pixel clock dynamic and constantly changing within it's allowed range and this will reduce the radiated emissions of the LCD. Is there a way that we can do this? The LCD allows the pixel clock to be between 42Mhz and 52MHz. We are using the 4.1.15 kernel.
Any thoughts on how to make the pixel clock cycle between 42MHz and 52MHz to reduce the average emissions?