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Is the internal Flash and Sram of the Kinetis KV5 family protected by ECC. If so where is the functionality described ? If not is it planned for future versions ?

Question asked by Carl Troili on Oct 3, 2017
Latest reply on Oct 10, 2017 by Fang Li

In the whitepaper "Exploring the ARM® Cortex®-M7 Core: Providing Adaptability for the Internet of Tomorrow" ECC memory is mentioned but I haven't seen any mentioning in the referance manual. If it is implemented in the KV5 family please state in what versions it is implemented and where the functionality is described. If it is not implemented right now please inform me when it is planned to be added.




Carl Troili