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i.MX6 Core/SOC power for DUAL

Question asked by Ian Dennis on Sep 18, 2017
Latest reply on Oct 6, 2017 by Ian Dennis



We are developing a custom i.MX6 board based on the NXP SDB, and would like to be able to fit a QUAD, DUAL or DUAL LITE processor depending on the application. There seems to be some disagreement in the documentation regarding the connection of the VDDARM23_IN and VDDARM23_CAP pins when using a DUAL processor. The general consensus seems to be that these should be separated from the VDDARM_IN and VDDARM_CAP nets and grounded for use with a DUAL processor, but this is not universally stated.  I suspect that it may be OK to leave them connected as for the QUAD and DL processors, but that optimum power draw may not be achieved in that case.  


The reason that this is an issue is that we are basing our board on the SDB layout, and it would be very inconvenient to include the jumper options to separate these nets (as shown in the hardware development guide, IMX6DQ6SDLHDG Rev. 210/2016) on that layout.


I wonder if someone could clarify this question once and for all? I'd also be grateful for clarification of the VDD_CACHE_CAP situation, which seems to be similar.