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[SPI] MOSI is changed from level '0' to level '1' before the falling edge happens

Question asked by Mohammed Aboelnasr on Aug 17, 2017
Latest reply on Aug 21, 2017 by xiangjun.rong

Greetings,

I am using KIT TRK-KEAZN64

 

I am configuring SPI peripheral as below; SPI0_C1 = BIT_SPIC0_SPE | BIT_SPIC0_MSTR | BIT_SPIC0_CPHA | BIT_SPIC0_CPOL; SPE = 1

=> Enable SPI system, MSTR = 1

=> Set SPI as master device, CPHA = 1

=> First edge at start of first data transfer cycle, CPOL = 1

=> SPI clock as active low (idle high).

 

So I am expecting MOSI to be changed at every falling edge of the clock. However, I had strange behavior which is in case of MOSI change from level '0' to level '1', this change occurs vefore the falling edge of clock happens. while it is working good when MOSI changes from level '1' to level '0'. This is illustrated more in the attached screenshots.

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