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LPC8xx USART synchronous mode SCLK edge

Question asked by Johan Myréen on Aug 11, 2017
Latest reply on Aug 23, 2017 by Johan Myréen

My question is about the USART module in the LPC8xx series microcontrollers. If the USART is transmitting in synchronous mode, does the signal transition on the rising or falling edge of SCLK, i.e. should the receiver sample it on the falling or rising edge of SCLK? I can't find this information in the User's Guide. The guide mentions CLKPOL (bit 12 in the USART config register), which determines the clock edge used by the receiver. Does this bit also affect the transmitter, or is there some other way of selecting the edge? If CLKPOL also affects the transmitter, I would assume the signal transition would happen on the opposite edge, so that similarly configured devices could communicate with each other.

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