I have drawn the schematic of i.MX6UL and PF3000(PMIC), by taking reference from Freescale EVK.
However now at the output of front end LDO, I am getting 3.4V, which should be 4.4V typical.
This net name mentioned as SYS_4V4 in the schematic.
There is 470pF capacitor between Source and Gate and I am getting 5V at both the ends.
Could you please help us on this issue at the earliest.