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What is the Maximum MIPI CSI2 bandwidth for 4 lanes ?

Question asked by Titus Stalin on May 23, 2017
Latest reply on Oct 26, 2017 by Titus Stalin

Hello Experts,

I would like to know the maximum achievable MIPI-CSI2 bandwidth with 4 lanes configuration for imx6 quad processor ?

I'm using 4 lanes MIPI configuration and able to achieve up to 750Mbps per lane, but imx6 guide mentioned 800Mbps per lane.

 

IMX6DQRM.pdf, page no 450.

 

One MIPI/CSI-2 port- IPU receives two components per cycle from the MIPI_CSI2
interface. The maximum bandwidth of the interface is as follows:
• 400MByte/sec for four data lanes configuration (800Mbps/lane)
• 375MByte/sec for 3 data lanes configuration (1000Mbps/lane)
• 250MByte/sec for 2 data lanes configuration (1000Mbps/lane)
• 125Mbyte/sec for 1 data lanes configuration (1000Mbps/lane)

 

So what is practically achievable MIPI-CSI2 bandwidth for 4 lanes ?

 

 

Thanks for your support.

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