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i.MX7 Clock tree undocumented divisors on PLL

Question asked by Siles on May 22, 2017
Latest reply on May 30, 2017 by Siles

Hi !

I'm currently working on a CCM driver for a i.MX7 board. My reference documentation if the refman Rev 0.1 and Linux source code, especially ./arch/arm/mach-imx/clk-imx7d.c from the Toradex SDK I got.

 

In the table: 5-11, Clock Root Table, we can see that ARM_A7_CLK_ROOT is plugged to ARM_PLL and AUDIO_PLL.

 

In the Clock Tree (figure 5.2.4) we can see multiple "orange box" divisor /2, especially between ARM_PLL / ARM_PLL_CLK and AUDIO/VIDEO_PLL and AUDIO/VIDEO_PLL_CLK, and then that ARM_A7_CLK_ROOT is using the PLL values divided by 2.

 

Linux source code makes no mention of these /2 between PLL and CLK_ROOT.

 

Following comment on https://community.nxp.com/message/904416?commentID=904416#comment-904416 (which did not answer my previous question, but I can't unflag the 'assumed answered' status...) I've been looking to FreeRTOS_iMX7D_1.0.1_LINUX from the i.MX7 without luck. I couldn't find a Linux BSP or more information.

The PLL are well-described but most of the clock roots (especially ENET and A7) seems missing. Any help to find a more precise BSP is welcome.

 

Can someone clarify what these /2 boxes are and if we have to take them into account when computing CLK_ROOT frequencies ?

 

Best,

V

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