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i.MX7 clock tre: ENET_REF_CLK_ROOT gates

Question asked by Vincent Siles on May 10, 2017
Latest reply on May 16, 2017 by Vincent Siles

Hi !

In the i.mx7 ref manual, we can see that there is not gates for the ENET1_REF_CLK_ROOT and ENET2_REF_CLK_ROOT in the Clock Tree (rev 0.1, Table 5.2.4 Clock Tree)


However in Linux source code (./arch/arm/mach-imx/clk-imx7d.c from Toradex SDK), we can see that both

ENET_REF_CLK_ROOT and ENET_TIME_CLK_ROOT are declared as gates:


clks[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_gate3("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28);
clks[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_gate3("enet1_time_cg", "enet1_time_src", base + 0xa780, 28);
clks[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_gate3("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28);
clks[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_gate3("enet2_time_cg", "enet2_time_src", base + 0xa880, 28);

Could someone clarify the situation and tell me if there is a gate or not at these locations ?