i.MX7 clock tre: ENET_REF_CLK_ROOT gates

[vsiles]

Hi !

In the i.mx7 ref manual, we can see that there is not gates for the ENET1_REF_CLK_ROOT and ENET2_REF_CLK_ROOT in the Clock Tree (rev 0.1, Table 5.2.4 Clock Tree)

However in Linux source code (./arch/arm/mach-imx/clk-imx7d.c from Toradex SDK), we can see that both

ENET_REF_CLK_ROOT and ENET_TIME_CLK_ROOT are declared as gates:

clks[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_gate3("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28);
clks[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_gate3("enet1_time_cg", "enet1_time_src", base + 0xa780, 28);
clks[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_gate3("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28);
clks[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_gate3("enet2_time_cg", "enet2_time_src", base + 0xa880, 28);
‍‍‍‍

Could someone clarify the situation and tell me if there is a gate or not at these locations ?

Best,

V.

[Carlos_Musich · Accepted solution]

Hi Vincent,

In 'Table 5-12. System Clocks and Gating' you can see that both, ENET1_TIME_ROOT and ENET2_TIME_ROOT are mapped to clk_enable_enet1 (CCGR112) and clk_enable_enet2 (CCGR113) respectively,

and this matches with Figure 5-15, so they do have Clock Gate Register.

On the other hand for ENET1_REF_CLK_ROOT and ENET2_REF_CLK_ROOT there are no Clock Gate registers, however there is an enable bit (bit 28) in Target Register that matches the API you pointed.

5.2.8 CCM Memory Map/Register Definition

Best regards,
TIC

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[vsiles]

Ok, I have now a better understanding of the distinction. Thank you !