I've found several unclear and confusing content.
1.) Chapter 9, clock source
1a.) Page 36, register "ICSSC", Bit CLKST.
Does not match with detailled description chapter 9.3.4 (page 129).
Looks like page 129, 130 is wrong or "oversized".
Also see page 126, figure 9-2. Totally wrong, there is no "external clock" for this device, and the shown selection bits are partly not available.
===> Clock Source chapter (9) needs excessive labor (rework).
1b) Question: Is ist required to setup any clock registers, or do power-on-reset values for ICSC1 / ICSC2 have proper state?
Is it required to wait for single CLKST bit (unless cleared).
1c) What about FLL "trim" stuff? Why FTRIM bit of ICSSC isn't setup in standard examples ?
2.) ADC, Chapter 8
2a) Page 97 ff. Same problem: Lot of channels, which are not available at this device.
See "Up to 28 analog inputs" page 99.
Why describe general HCS08 things in special QD4/2 datasheet ??).
Simple delete the "N/A" part of the table!
2b) Other important (?) things are not explained, e.g. if "BGBE" bit is required or not, should be enabled once or de-activated after "Bandgap" conversion, etc.
I think, there are (several) more unclear points in other parts of the datasheet.
Rework for datasheet is strongly recommented and necessary.