From the data sheet, it seem i have to wait for 300~500ms when erase DFLASH.
What is the risk if i open the external interrupts after enable EHV , or non-blocking
Hi, it does not mean user would have to set up this wait time manually. After starting erase operation application polls MCR[DONE] bit. However erase time may differ from piece-to-piece and it is also given by aging of flash memory.
in this p time need to pay attention to what?
Is there a special document to introduce this?
as usually：close external interrupts => EHV=1 => waiting for DONE => EHV=0 => open external interrupts；
change ：close external interrupts => EHV=1 => open external interrupts=> polls MCR[DONE] => EHV=0；
We need to assess the risk of change
Hi, there is a risk of read-while-write operation in case user software wants to read from the memory during erase/program. It would lead either in bus error or execution stall (according to RWWC, on this device stalls by default).
A solution is to have interrupt vector table and interrupt/exception service routine placed in SRAM.
Even if interrupt/exception service routine are placed in FLASH that would be in the CFlash not in teh DFlash ...
Yes, you are right. I have somehow forgot we are talking about DFLASH. In case case it should be OK unless interrupt service routine does not access DFLASH.
Retrieving data ...