I am currently developing an application on an LPC54102 clocked by its IRC (12 MHz). The application is almost coded now, and recently I started to implement the PLL in order to get higher clock frequencies, like 24, 36, 48, ... 96 MHz.
I am using the CLKOUT pin to monitor the main_clock and I have verified that I generate precisely each integer multiple of 12 MHz, up to 96 MHz. I have taken care to have a CCO frequency comprized within the 75 / 150 MHz limits. The PLL works in "normal mode". The PLL locks immediately and I do no see any visible jitter on the CLKOUT signal.
The target is an LPCxpresso 54102 board. I do not use the LPCopen library.
As long as I stay with 12 or 24 MHz, the micro works fine, but as soon as I try to use any higher frequency, it crashes as soon as I switch to the PLL clock.
I am wondering if there is maybe an additional configuration, related to the power management to perform in order to gain access to higher core frequencies ? I did not find anything relevant until now.
Thank you for your support.