AnsweredAssumed Answered

P5020 Multibit ECC

Question asked by Timothy Park on Mar 9, 2017
Latest reply on Mar 28, 2017 by Bulat Karymov

Hello,

 

I am trying to test the multi-bit ECC capability on the P5020, however, I seem to be running into an issue where I hit multiple machine check errors after the first multi-bit ecc is handled. I have the following set up to inject the multi-bit ecc and also to handle the machine check exception to follow:

 

DDR_ERR_DISABLE = 0

DDR_SDRAM_CFG[ECC_EN] = 1

DDR_ERR_INJECT_LO = 0x00000003

DDR_ERR_INJECT[EIEN] = 1

 

IVOR1 is set to handle the machine check exception by rolling up MCSRR0 to the next instruction once the rfmci instruction is called.

 

After the first multi-bit ecc is handled the injection is turned off as such: DDR_ERR_INJECT[EIEN] = 0.

 

It is after this where every instruction step will trigger a multi-bit error and it keeps vectoring off to IVOR1.

 

Please let me know what else I should be doing.

 

Thanks,

Tim

Outcomes