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LS102x: QUICC/UCC UART

Question asked by konradgräfe on Feb 21, 2017
Latest reply on Mar 8, 2017 by konradgräfe

Hello,

 

I am having a hard time getting the UCC UART running on my custom board with a LS1020A CPU. I use the Linux kernel from Freescale SDK version fsl-sdk-v2.0-1701 with a custom mainline U-Boot.

The driver gets loaded but I can neither send nor receive from the ttyQE devices. When sending, the driver takes some seconds before raising Shutdown timeout to the kernel log. When receiving just nothing happens.

 

From what I saw from some debug messages I added, it seems that the QUICC engine never clears the BD_SC_READY bit in the buffer descriptors and the driver does not receive any interrupts.

 

This is the important part of my device tree:

/dts-v1/;
#include "ls1021a.dtsi"
...
&uqe {
    ucc1: ucc@2000 {
        device_type = "serial";
        compatible = "ucc_uart";
        port-number = <1>;
        rx-clock-name = "brg1";
        tx-clock-name = "brg1";
    };

    ucc2: ucc@2200 {
        device_type = "serial";
        compatible = "ucc_uart";
        port-number = <3>;
        rx-clock-name = "brg2";
        tx-clock-name = "brg2";
    };
};

and this is the RCW (QE_TDMA and QE_TDMB should both be 2):

Reset Configuration Word (RCW):
       00000000: 0608000a 00000000 00000000 00000000
       00000010: 80000000 00407900 60044a00 21046000
       00000020: 00000000 00000000 00000000 08000700
       00000030: 20124900 04091340 00000000 00000000

 

What could I have missed? Please let me know if you need more information.

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