I am trying to understand how the PBL is transitioning from PBI instruction into BOOT startup location which reside in NOR FLASH?
Here is the RCW + PBI from the T1042RDB (T1042 Reference Design Board)
e8000000: aa55aa55 010e0100 0c18000e 0e000000 -> RCW preamble
e8000010: 00000000 00000000 86000002 40000002
e8000020: ec027000 01000000 00000000 00000000
e8000030: 00000000 00030810 00000000 01fe580f
e8000040: 00000000 00000000 09250100 00000400 -> PBI commands started at "e800004c" CCSR write 0x0000_0400 to address 0x25_0100
e8000050: 09250108 00002000 08138040 89564dd5 -> CCSR write 0x0000_2000 to address 0x25_0108 and PBI command for CRC check
How the PBI CCSR writes in the above are used to transition into NOR Flash u-boot start address?
Just for additional information, I have included possible relevant snip of the document I have been looking.
Here is the memory map from the QorIQ SDK v2.0-1701 Documentation document
Page #324 section 220.127.116.11 System Memory Map in this document it specify the memory map as follow:
Table 94. NOR flash memory map in the QorIQ SDK v2.0-1701 document specify the NOR flash as follow: