AnsweredAssumed Answered

i.MX6 and TZC380 Action

Question asked by Vincent Siles on Jan 9, 2017
Latest reply on Jan 11, 2017 by Vincent Siles

Hi !

I have configured the TZASC of my i.MX6q board to protect the last 256 Mb (from 0x4000_0000 to 0x4800_0000) of RAM from the Normal World. First, I configured the TZASC Action register with the value 2, to be notified via IRQ of the accesses but just ignore them silently (no fault). I get a notification during u-boot sequence, so I'm trying to understand what's wrong.

Since I didn't manage to find the culprit, I decided to change the action to 1, in order to trigger a pagefault (DECERR) (or at least that's how I understand it), and in this configuration, u-boot works fine, it doesn't seem to get an exception.

Once u-boot is done, I can see that the fault address register of the TZASC is no longer 0, but a secure address, so something happened, but no fault seems to have been created.


Is my understanding of the TZASC action register correct ? Is there a way to get the address of the exact instruction which is trying to access the secure part of the DDR ?



PS: for your information, the AXI ID I get are either 0x18 or 0x19, which seems to be ARM_S0/ARM_S1, but I don't know at all what they stand for.