The K64 reference manual describes the CHF channel interrupt flag in CnSC as:
Set by hardware when an event occurs on the channel. CHF is cleared by reading the CSC register while CHnF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect. If another event occurs between the read and write operations, the write operation has no effect; therefore, CHF remains set indicating an event has occurred. In this case a CHF interrupt request is not lost due to the clearing sequence for a previous CHF.
This implies that no interrupts will be dropped that occur between reading the interrupt flag and resetting it by writing a 1.
However, the processor expert component interacts with this register three times. It is first read to check the status of the flag, the ISR is called, then the &= operation is used to reset the flag, effectively a read operation immediately followed by a write.
My question is does the description in the datasheet guarantee no loss of interrupt events between the first read operation and the write, or only between the second read and the write?