In an application a costumer will use an MPC8260 processor and a 256Mbyte SDRAM (4 x MT48LC32M16A2 parallel) via the existing SDRAM interface. The SDRAM will operate at a frequency of 50MHz. (The SDRAM is already controlled in another application with another processor and should be used in this case again if possible.) The "self-refresh" function is important. From the data sheets I could see that the interface of the processor does not provide a CKE pin, which is used by the SDRAM. So the question whether the specified SDRAM is compatible with the MPC8260 SDRAM interface and how the corresponding application would be implemented? Or is there an alternative SDRAM that is more suitable for this purpose? Many thanks in advance.
According to the datasheet of the SDRAM, however, the CKE pin would have to be actively controlled, which is why I suspect that a 1KOhm resistor should not be sufficient for VDD?
Enclosed are the sections from the data sheet of the SDRAM (MT48LC32M16A2).
There is no way to implement Self Refresh mode for SDRAM without external glue logic. The problem is that Self Refresh command couldn't be implemented without synchronous (with SDRAM clock) control of the Clock Enable SDRAM input (CKE).
Below is possible variant of the "glue logic" which allows to put SDRAM into Self Refresh mode. During normal operation Output port pin level is high. When Self Refresh is required, Output port pin level is set to low. In this case CKE will be lowered synchronously with SDRAMCS.
Do you have any experience with this logic acc. self refresh mode in SDRAM? If yes, could you give me please the Info which SDRAM did you use.
And are you sure, that this logic will work in this case? I am not sure if the timing can handle this mode.....
> Do you have any experience with this logic acc. self refresh mode in SDRAM?
Unfortunately, no.
The MT48LC32M16A2 can be used.
The CKE pin can be connected to VDD through 1 kOhm resistor.