I am using LPC4357.
We would like to use below mapping. Is it possible?
M4 core: 768kByte (BANKA 512kB BANKB 256kB)
M0 core: 256kbyte (BANKB 256kB)
Yes, it can be done, BUT you will have serious bus contention on the shared Flash (Bank B) that will slow down both cores. It is much much better to have the M0 run from a completely separate memory bank - in your case one of the RAM banks.
See this FAQ: LPC43xx Cortex-M4 / M0 Multicore Applications
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