We are working on S32K144 board,we are able to transmit data and also its visible on CANalyzer trace window i.e arbitration phase at nominal bit rate and data phase at higher bit rate, But unable to receive data when we transmit it from IG window of CANalyzer with BRS bit SET. We are able to receive 64 bytes of data with BRS bit RESET. Below are the inputs given
1. Clock source is BUS clock with 40Mhz frequency
2. Rx_Fifo = false
3. Fd_Enable = true
4. /* Macros to Configure Tx message buffer */
#define CANTX_DATALENGTH 64u
#define CANTX_FDENABLE 1u
#define CANTX_FDPADDING 0X00u
#define CANTX_ENABLEBRS 1u
The above mentioned values are passed in the function "FLEXCAN_DRV_ConfigTxMb"
/* Macros to Configure Rx message buffer */
#define CANRX_DATALENGTH 64u
#define CANRX_FDENABLE 1u
#define CANRX_FDPADDING 0u
#define CANRX_ENABLEBRS 1u
The above mentioned values are passed in the function "FLEXCAN_DRV_ConfigRxMb"
5. /* Macros for CAN_Baudrate setting for (CAN0->CBT with 500Kbps nominal bit rate) */
#define BAUDRATE_PROPSEG 46u
#define BAUDRATE_PHASESEG1 15u
#define BAUDRATE_PHASESEG2 15u
#define BAUDRATE_PREDIVIDER 0x00u
#define BAUDRATE_RJUMPWIDTH 15u
/* Macros for CAN_FD_Baudrate setting for (CAN0->FDCBT with 2Mbps higher bit rate)*/
#define BAUDRATE_PROPSEGFD 7u
#define BAUDRATE_PHASESEG1FD 7u
#define BAUDRATE_PHASESEG2FD 3u
#define BAUDRATE_PREDIVIDERFD 0x00u
#define BAUDRATE_RJUMPWIDTHFD 3u
6. BITBAND_ACCESS32(&(base->FDCTRL), CAN_FDCTRL_TDCEN_SHIFT) = (0x0);
BITBAND_ACCESS32(&(base->FDCTRL), CAN_FDCTRL_TDCOFF_SHIFT) = (0x1);
BITBAND_ACCESS32(&(base->CTRL2), CAN_CTRL2_STFCNTEN_SHIFT) = (0x0);
I tried making TDCEN bit and STFCNTEN bit SET also changed the value of TDCOFF as 5,but TDCOFF value is not getting updated.What should be the values for the above bits?
7. Inside "FLEXCAN_HAL_SetTxMsgBuff" function,Below conditions have been checked
if (cs->fd_enable == 1) and if (cs->enable_brs == 1)
8. Inside"FLEXCAN_HAL_SetRxMsgBuff" function,Below conditions have not been checked
if (cs->fd_enable == 1) and if (cs->enable_brs == 1),however I tried by adding these conditions as well and made EDL and BRS bit set.But still I am getting Error interrupt for Reception with Stuff and Form error SET.
kindly let me know what additional changes need to be made for reception process.