We are using an I2C communication path on an i.MX6 Solo, via the i2c2 module.
It is a single master (i.MX6), single device topology, with a rate of 100 kbit/s. Communication consists mainly in reading the content of an EEPROM, reading the state of a few IOs, and sometimes program some IOs. Software environment is Yocto Dizzy.
For various reasons, it is important that SCL conforms to the I2C standard in that it remains in the HIGH state when not toggling.
But it appears that i.MX6's I2C leaves SCL LOW between some 8-bit words, sometimes for a time as long as several hundreds of microseconds.
Here is my question:
Is this a known behaviour? Is there a way of making sure that SCL never stays LOW within a data transfer?
Thank you for your help,