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FTM - Board compatibility / working

Question asked by nadreoh on Oct 26, 2016
Latest reply on Nov 3, 2016 by nadreoh

Dear support Team,

 

Context:

I'm trying to use my FlexTimer module on DevBoard RevB (S32K144).

I also have the datasheet from Aug. 2015 and the new one from Aug. 2016.

I work with the IAR IDE, using the IAR library and a J-LINK Debugger.

 

My questions:

Is the FTM module able to work on my board (RevB)?

Or should I wait for the new board (from 2016)?

Or did I missed one or more configurations in my Code?

 

Note (from datasheet aug. 2015), page 801:

The Global Load mechanism of FTM module is not supported on this device.

 

My configurations:

It seems to approximately work when trying to Flash Code after several times and using:

• SOSC at 8MHz

• SPLL at 32MHz, that is also the System clock source (SYSclk/COREclk/BUSclk/SLOWclk set to 32MHz)

• SIRC / FIRC are disable

• FTM[0..3] clock source is SOSC_DIV1 (8MHz)

• PIN PTD15 / PTB5 set on Alteration2 to use FTM0_CH0 and FTM0_CH5 (same FTM0 Signal on this two PINs / channels)

• Need to generate a 4MHz PWM with Alpha, duty cycle = 50%

 

My Code (only for FTM):

 Following the datasheet 2016 advice (page 1086) for my configuration. Uncalled Registers are set as Default.

 

int main (void)

{

   Disable WatchDog

   Oscillators initialization

   Ports initialization

 

  /* Needs to set MOD to get only one incrementation */

  FTM0_MOD |= FTM_MOD_MOD(0x0001u);

 

  /* Needs to set Channels MODES to edge-aligned PWM */
  FTM0_C0SC |= FTM_C0SC_MSB(1u);
  FTM0_C0SC |= FTM_C0SC_ELSA(1u);
  FTM0_C5SC |= FTM_C5SC_MSB(1u);
  FTM0_C5SC |= FTM_C5SC_ELSA(1u);
 

  /* Needs to set CnV to get flag when Counter value is 1 */
  FTM0_C0V |= FTM_C0V_VAL(0x0001u);
  FTM0_C5V |= FTM_C5V_VAL(0x0001u);
 

  /* Others configurations... */
  FTM0_CNT |= FTM_CNT_COUNT(0x0000u);
  FTM0_SC |= FTM_SC_CLKS(3u);
  FTM0_SYNC |= FTM_SYNC_SYNCHOM(1u);
  FTM0_SYNCONF |= FTM_SYNCONF_SWOM(1u);
  FTM0_SYNCONF |= FTM_SYNCONF_SWRSTCNT(1u);
  FTM0_SYNCONF |= FTM_SYNCONF_SYNCMODE(1u) ;
 

  /* Enable FTM0_CH0 and FTM0_cH5 */
  FTM0_OUTMASK |= FTM_OUTMASK_CH7OM(1u);
  FTM0_OUTMASK |= FTM_OUTMASK_CH6OM(1u);
  FTM0_OUTMASK |= FTM_OUTMASK_CH5OM(0u);
  FTM0_OUTMASK |= FTM_OUTMASK_CH4OM(1u);
  FTM0_OUTMASK |= FTM_OUTMASK_CH3OM(1u);
  FTM0_OUTMASK |= FTM_OUTMASK_CH2OM(1u);
  FTM0_OUTMASK |= FTM_OUTMASK_CH1OM(1u);
  FTM0_OUTMASK |= FTM_OUTMASK_CH0OM(0u);
 

  /* Active matching channels */
  FTM0_SYNC |= FTM_SYNC_SWSYNC(1u);
  FTM0_SC |= FTM_SC_PWMEN0(1u);
  FTM0_SC |= FTM_SC_PWMEN5(1u);

 

Main Loop

 

Best regards,

Nadreoh

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