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MPC8548 eTSEC 104 erratum

Question asked by Robert Bracero on Oct 26, 2016
Latest reply on Nov 2, 2016 by bpe

For the MPC8548 eTSEC 104 erratum, is it possible to get clarification on what is considered a low platform to Rx_clk ratio and slow memory system?

 

The SBC that we are supporting has a 400 MHz platform clock, a DDR2 frequency of 200 MHz, and the eTSEC is in MII mode running at a max speed of 100 Mbps. Is it safe to assume that eTSEC 104 is not applicable in this case?

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