i.MX6solo wdog1 failed to reset spi-nor board

[jasperzhang]

Hi All

We came across a wdog1 usage issue on our i.MX6Solo customized board. It can be summarized as simple as followings:

1. If we don't define spi-nor chip select gpio in device tree, wdog1 works.
2. If we define spi-nor chip select gpio in device tree, wdog1 doesn't work.

The kernel version is 4.01.15. If we define the cs-gpios as below, wdog1 failed.

&ecspi1 {
   fsl,spi-num-chipselects = <1>;
   cs-gpios = <&gpio3 19 0>; /* EIM_D19/ECSP1_SS1 */
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
   status = "okay";

   flash: m25p80@0 {
      #address-cells = <1>;
      #size-cells = <1>;
      compatible = "micron,n25q512a";
      spi-max-frequency = <20000000>;
      reg = <0>;
   };
};

We want to use wdog1 to reset i.MX6 SoC only. We don't need any watchdog reset output signals.

Spi-nor is the only flash storage on our board. It uses single spi port-1 (pad EIM_D16/17/18) and the chip select is EIM_D19/ECSPI1_SS1.

The ROM code can find and boot u-boot from the spi-nor and u-boot can boot kernel from spi-nor or through NFS.

We use NFS to verify wdog1.

When wdog1 works, it can reset SoC and we can see the u-boot message in the console again.

The working device tree looks like followings:

&ecspi1 {
   fsl,spi-num-chipselects = <1>;
   cs-gpios = <&gpio3 25 0>; /* remove this line and wdog1 works too */
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
   status = "okay";

   flash: m25p80@0 {
      #address-cells = <1>;
      #size-cells = <1>;
      compatible = "micron,n25q512a";
      spi-max-frequency = <20000000>;
      reg = <0>;
   };
};

We modified our board and tried to use another pin, EIM_D25/ECSP1_SS3, as chip select and we got the same result. This time, "cs-gpios = <&gpio3 19 0>;" in device tree made wdog1 worked and "cs-gpios = <&gpio3 25 0>;" didn't.

Any input is appreciated.

JasperZ

[igorpadykov]

Hi Jasper

only available option to reboot reliably is to reset whole

board, including PMIC as in sabre sd schematic spf-27392 p.21

with U507 buffer. In general you can debug it using AN4553

Using Open Source Debugging Tools for Linux on i.MX Processors

http://cache.nxp.com/files/32bit/doc/app_note/AN4553.pdf 

Best regards
igor
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[jamesdavis]

Hi Igor,

Here is some more detail. On this Design, the i.MX6Solo boots from SPI NOR Flash, and then the Kernel is loaded via Ethernet. There are no problems at this point.

Then a Warm reset is done and the i.MX6Solo attempts to boot from the SPI NOR Flash again and fails. The failure mechanism appears to be defining in software the chip select pin that the SPI NOR Flash is connected to. In this particular case the SPI NOR chip select is EIM_D19/ECSPI1_SS1.

Interestingly, if the SPI NOR Flash is changed to a SD Card, there is no problem with a Warm reset.

Can you use SPI NOR Flash for Booting after you have loaded the Kernel and then do a Warm reset?

Is there an issue with the state of the pins connected to the SPI NOR Flash when you do a Warm reset?

Thanks,

James

[igorpadykov]

Hi James

setting "cs-gpios" may configure EIM_D19 as GPIO (ALT5), while for spi boot

ALT1 selection is needed.

Only reliable way to reboot is whole board reset including pmic.

Also for SPI NOR Flash case one can attach oscilloscope and test

signals on SPI NOR Flash (compare them with successful boot case),

also refer to sect.8.5.4.1 Serial ROM eFUSE Configuration i.MX6SDL

Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf

Difference between warm reset from other reset types can be found on

sect.60.6.1.1 Reset inputs and outputs

Best regards
igor