MFRC522 strange behaviour

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MFRC522 strange behaviour

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dietrichwall
Contributor II

Hello,

I have to implement an authentication application with an MFRC522 ver 02 Mifare reader. The reader is connected via I2C to a MSP430 Microcontroller. The first tests were successfull, i´m able to read the Version register. But reading other registers returns values which are not documented in this way. For example: reading the CommandReg register returns 0x3F, Datasheet mentions a reset value of 0x20.

Write accesses into internal Registers are also accepted and acknowledged from the chip. But when i´m trying to read out the written values, the initial values do not change. 

The only register value that seems to be ok is the VersionReg Register(Adress: 0x37, Value 0x92)

What could be the reason for this behaviour?

Thx in advance

Dietrich

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Kan_Li
NXP TechSupport
NXP TechSupport

Hi Dietrich,

Would you please give a register dump from your side? and have you sent any command to RC522 before the reading? Please kindly help to clarify. Thanks for your patience!


Have a great day,
Kan Li
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dietrichwall
Contributor II

Hi Kan_Li,

I´ve made 3 Register Dumps. One before writing Reset Command in Commandregister, one right after writing it and the third with a delay of 1 second between the Reset command and reading the registers. The values are hexadezimal notated without leading zeros. Unfortunately I do not understand how to upload files in this forum, so I have to paste data as text.

Before Reset:

Reg: 0, Val: 0
Reg: 1, Val: 3f
Reg: 2, Val: 80
Reg: 3, Val: 0
Reg: 4, Val: 0
Reg: 5, Val: 8
Reg: 6, Val: 0
Reg: 7, Val: 28
Reg: 8, Val: 0
FIFO 0: 31
FIFO 1: 31
FIFO 2: 31
FIFO 3: 31
FIFO 4: 31
FIFO 5: 31
FIFO 6: 31
FIFO 7: 31
FIFO 8: 31
FIFO 9: 31
FIFO 10: 31
FIFO 11: 31
FIFO 12: 31
FIFO 13: 31
FIFO 14: 31
FIFO 15: 31
FIFO 16: 31
FIFO 17: 31
FIFO 18: 31
FIFO 19: 31
FIFO 20: 31
FIFO 21: 31
FIFO 22: 31
FIFO 23: 31
FIFO 24: 31
FIFO 25: 31
FIFO 26: 31
FIFO 27: 31
FIFO 28: 31
FIFO 29: 31
FIFO 30: 31
FIFO 31: 31
FIFO 32: 31
FIFO 33: 31
FIFO 34: 31
FIFO 35: 31
FIFO 36: 31
FIFO 37: 31
FIFO 38: 31
FIFO 39: 31
FIFO 40: 31
FIFO 41: 31
FIFO 42: 31
FIFO 43: 31
FIFO 44: 31
FIFO 45: 31
FIFO 46: 31
FIFO 47: 31
FIFO 48: 31
FIFO 49: 31
FIFO 50: 31
FIFO 51: 31
FIFO 52: 31
FIFO 53: 31
FIFO 54: 31
FIFO 55: 31
FIFO 56: 31
FIFO 57: 31
FIFO 58: 31
FIFO 59: 31
FIFO 60: 31
FIFO 61: 31
FIFO 62: 31
FIFO 63: 31
Reg: a, Val: 0
Reg: b, Val: 8
Reg: c, Val: 34
Reg: d, Val: 0
Reg: e, Val: a5
Reg: f, Val: 0
Reg: 10, Val: 0
Reg: 11, Val: 3f
Reg: 12, Val: 0
Reg: 13, Val: 0
Reg: 14, Val: 80
Reg: 15, Val: 0
Reg: 16, Val: 10
Reg: 17, Val: 84
Reg: 18, Val: 84
Reg: 19, Val: 4d
Reg: 1a, Val: 0
Reg: 1b, Val: 0
Reg: 1c, Val: 62
Reg: 1d, Val: 0
Reg: 1e, Val: 0
Reg: 1f, Val: eb
Reg: 20, Val: 0
Reg: 21, Val: fb
Reg: 22, Val: ff
Reg: 23, Val: 88
Reg: 24, Val: 26
Reg: 25, Val: 87
Reg: 26, Val: 48
Reg: 27, Val: 88
Reg: 28, Val: 20
Reg: 29, Val: 20
Reg: 2a, Val: 0
Reg: 2b, Val: 0
Reg: 2c, Val: 0
Reg: 2d, Val: 0
Reg: 2e, Val: e0
Reg: 2f, Val: a6
Reg: 30, Val: 0
Reg: 31, Val: 0
Reg: 32, Val: 0
Reg: 33, Val: 80
Reg: 34, Val: 0
Reg: 35, Val: 4
Reg: 36, Val: 40
Reg: 37, Val: 92
Reg: 38, Val: 0
Reg: 39, Val: 24
Reg: 3a, Val: 0
Reg: 3b, Val: 0
Reg: 3c, Val: ff
Reg: 3d, Val: 0
Reg: 3e, Val: 3
Reg: 3f, Val: 0

After Reset no delay:

Reg: 0, Val: 0
Reg: 1, Val: 3f
Reg: 2, Val: 80
Reg: 3, Val: 0
Reg: 4, Val: 74
Reg: 5, Val: c
Reg: 6, Val: 0
Reg: 7, Val: 25
Reg: 8, Val: 4
FIFO 0: 0
FIFO 1: 0
FIFO 2: 0
FIFO 3: 0
FIFO 4: 0
FIFO 5: 0
FIFO 6: 0
FIFO 7: 0
FIFO 8: 0
FIFO 9: 0
FIFO 10: 0
FIFO 11: 0
FIFO 12: 0
FIFO 13: 0
FIFO 14: 0
FIFO 15: 0
FIFO 16: 0
FIFO 17: 0
FIFO 18: 0
FIFO 19: 0
FIFO 20: 0
FIFO 21: 0
FIFO 22: 0
FIFO 23: 0
FIFO 24: 0
FIFO 25: 0
FIFO 26: 0
FIFO 27: 0
FIFO 28: 0
FIFO 29: 0
FIFO 30: 0
FIFO 31: 0
FIFO 32: 0
FIFO 33: 0
FIFO 34: 0
FIFO 35: 0
FIFO 36: 0
FIFO 37: 0
FIFO 38: 0
FIFO 39: 0
FIFO 40: 0
FIFO 41: 0
FIFO 42: 0
FIFO 43: 0
FIFO 44: 0
FIFO 45: 0
FIFO 46: 0
FIFO 47: 0
FIFO 48: 0
FIFO 49: 0
FIFO 50: 0
FIFO 51: 0
FIFO 52: 0
FIFO 53: 0
FIFO 54: 0
FIFO 55: 0
FIFO 56: 0
FIFO 57: 0
FIFO 58: 0
FIFO 59: 0
FIFO 60: 0
FIFO 61: 0
FIFO 62: 0
FIFO 63: 0
Reg: a, Val: 0
Reg: b, Val: 8
Reg: c, Val: 30
Reg: d, Val: 0
Reg: e, Val: a0
Reg: f, Val: 0
Reg: 10, Val: 0
Reg: 11, Val: 3f
Reg: 12, Val: 0
Reg: 13, Val: 0
Reg: 14, Val: 80
Reg: 15, Val: 0
Reg: 16, Val: 10
Reg: 17, Val: 84
Reg: 18, Val: 84
Reg: 19, Val: 4d
Reg: 1a, Val: 0
Reg: 1b, Val: 0
Reg: 1c, Val: 66
Reg: 1d, Val: 0
Reg: 1e, Val: 0
Reg: 1f, Val: eb
Reg: 20, Val: 0
Reg: 21, Val: 62
Reg: 22, Val: 3a
Reg: 23, Val: 88
Reg: 24, Val: 26
Reg: 25, Val: 87
Reg: 26, Val: 48
Reg: 27, Val: 88
Reg: 28, Val: 20
Reg: 29, Val: 20
Reg: 2a, Val: 0
Reg: 2b, Val: 0
Reg: 2c, Val: 0
Reg: 2d, Val: 0
Reg: 2e, Val: 0
Reg: 2f, Val: 0
Reg: 30, Val: 0
Reg: 31, Val: 0
Reg: 32, Val: 0
Reg: 33, Val: 80
Reg: 34, Val: 0
Reg: 35, Val: 9
Reg: 36, Val: 40
Reg: 37, Val: 92
Reg: 38, Val: 0
Reg: 39, Val: 24
Reg: 3a, Val: 0
Reg: 3b, Val: ff
Reg: 3c, Val: ff
Reg: 3d, Val: 0
Reg: 3e, Val: 3
Reg: 3f, Val: 0

After Reset with delay:

Reg: 0, Val: 0
Reg: 1, Val: 3f
Reg: 2, Val: 80
Reg: 3, Val: 0
Reg: 4, Val: 0
Reg: 5, Val: 8
Reg: 6, Val: 0
Reg: 7, Val: 28
Reg: 8, Val: 0
FIFO 0: 31
FIFO 1: 31
FIFO 2: 31
FIFO 3: 31
FIFO 4: 31
FIFO 5: 31
FIFO 6: 31
FIFO 7: 31
FIFO 8: 31
FIFO 9: 31
FIFO 10: 31
FIFO 11: 31
FIFO 12: 31
FIFO 13: 31
FIFO 14: 31
FIFO 15: 31
FIFO 16: 31
FIFO 17: 31
FIFO 18: 31
FIFO 19: 31
FIFO 20: 31
FIFO 21: 31
FIFO 22: 31
FIFO 23: 31
FIFO 24: 31
FIFO 25: 31
FIFO 26: 31
FIFO 27: 31
FIFO 28: 31
FIFO 29: 31
FIFO 30: 31
FIFO 31: 31
FIFO 32: 31
FIFO 33: 31
FIFO 34: 31
FIFO 35: 31
FIFO 36: 31
FIFO 37: 31
FIFO 38: 31
FIFO 39: 31
FIFO 40: 31
FIFO 41: 31
FIFO 42: 31
FIFO 43: 31
FIFO 44: 31
FIFO 45: 31
FIFO 46: 31
FIFO 47: 31
FIFO 48: 31
FIFO 49: 31
FIFO 50: 31
FIFO 51: 31
FIFO 52: 31
FIFO 53: 31
FIFO 54: 31
FIFO 55: 31
FIFO 56: 31
FIFO 57: 31
FIFO 58: 31
FIFO 59: 31
FIFO 60: 31
FIFO 61: 31
FIFO 62: 31
FIFO 63: 31
Reg: a, Val: 0
Reg: b, Val: 8
Reg: c, Val: 34
Reg: d, Val: 0
Reg: e, Val: a5
Reg: f, Val: 0
Reg: 10, Val: 0
Reg: 11, Val: 3f
Reg: 12, Val: 0
Reg: 13, Val: 0
Reg: 14, Val: 80
Reg: 15, Val: 0
Reg: 16, Val: 10
Reg: 17, Val: 84
Reg: 18, Val: 84
Reg: 19, Val: 4d
Reg: 1a, Val: 0
Reg: 1b, Val: 0
Reg: 1c, Val: 62
Reg: 1d, Val: 0
Reg: 1e, Val: 0
Reg: 1f, Val: eb
Reg: 20, Val: 0
Reg: 21, Val: fb
Reg: 22, Val: ff
Reg: 23, Val: 88
Reg: 24, Val: 26
Reg: 25, Val: 87
Reg: 26, Val: 48
Reg: 27, Val: 88
Reg: 28, Val: 20
Reg: 29, Val: 20
Reg: 2a, Val: 0
Reg: 2b, Val: 0
Reg: 2c, Val: 0
Reg: 2d, Val: 0
Reg: 2e, Val: e0
Reg: 2f, Val: a6
Reg: 30, Val: 0
Reg: 31, Val: 0
Reg: 32, Val: 0
Reg: 33, Val: 80
Reg: 34, Val: 0
Reg: 35, Val: 4
Reg: 36, Val: 40
Reg: 37, Val: 92
Reg: 38, Val: 0
Reg: 39, Val: 24
Reg: 3a, Val: 0
Reg: 3b, Val: 0
Reg: 3c, Val: ff
Reg: 3d, Val: 0
Reg: 3e, Val: 3
Reg: 3f, Val: 0

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Kan_Li
NXP TechSupport
NXP TechSupport

Hi Dietrich,

Thanks for the information! I am checking with our AE team for this issue, and will let you know when I have any more information.

Thanks for your patience!

Best regards,

Kan

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dietrichwall
Contributor II

Hi Kan_Li,

Thanks for your efforts, we have found the reason for this. It was a wrong placed oscilator on the PCB. Which seems also to describe the read register values.

Best regards, 

Dietrich

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