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T1040 DDR3 ECC Strategy

Question asked by Adam Garrison on Sep 27, 2016
Latest reply on Sep 27, 2016 by Serguei Podiatchev

I am using a 72b DDR3 interface on the T1040.  Using the 72 bit interface normally locks me into using x8 ICs because it only has 8 bits of ECC. What I’m curious about though, would be the possibility of using x16 chips to save space. I could see two possibilities, and I’m just not enough of an expert on SDRAM to know if this would work or just cause more problems than it’s worth. I  would either propose:

   -Use Qty 5 x16 ICs, leaving the upper 8 data bits of the ECC IC unconnected or grounded.

   -Use Qty 4 x16 ICs, and Qty 1 x8 IC for ECC

 

I’m wondering if either of these schemes would work, and if so, which would be preferred?

 Thank you,

Adam

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