How to use Pass Through with SRAM mapping (section 11.3)

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

How to use Pass Through with SRAM mapping (section 11.3)

1,130 Views
kfchoong
Contributor IV

Hi Sir / Madam,

I need your help in configuring Pass Through which can be use in 2 way communication.  Millions of thanks.

I would like to configure pass through and use the SRAM mapping feature of NTAG I2C 1K.  With reference to NT3H1101_1201.pdf, Page 52/65, Section 11.3.1 SRAM buffer mapping, it says that "  In Pass-through mode, the SRAM is mirrored to pages F0h to FFh sector 0 for the NTAG I²C 1k "  .  Does this means that after I configure Pass Through (session register, NC_REG byte, bit 6 - PTHRU_ON_OFF = 1b) , what I wrote to SRAM (Block address 0xF8 to 0xFB) from I2C interface will be automatically mirrored to location, starting at 0xF0 ?  And the data in block 0xF0 can be retrieve by another NFC device, for example device B ?  Also, device B can write to this location (block address 0xF0) , and then data in this location can be access by I2C interface, and then to Microcontroller ? 

 I have configured Pass Through and then write to SRAM,  then I use another device to scan the NFC of this device and retrieve its data.  From my IDE, I read through all 255 pages of data,  the portion at page 0xF0 (from RF perspective)  is all 0x00, which is not correct.  Please help.

Thank you for your advice.

Cheers,

KF Choong

0 Kudos
Reply
5 Replies

675 Views
kfchoong
Contributor IV

Hi Sir / Madam,

Have found the solution, write 0x7F instead of 0x41 to NC_REG. 

Thanks a million.

Cheers,

KF Choong

0 Kudos
Reply

675 Views
kfchoong
Contributor IV

Hi Sir / Madam,

With the presence of RF wave at RF interface, I have tried to write to SRAM before and after configure Pass Through.  Write to SRAM Before configure Pass Through is a success.  Write to SRAM after configure Pass Through is a failure.  For the automatically mapped SRAM to location 0xF0 after configure Pass Through,  I am not able to Read from this location (0xF0) from I2C interface, with and without Pass Through.  May I know how can I can write to SRAM (from I2C interface) after configure Pass Through ?  May I know how can I read (from I2C interface) from the SRAM Mapped location (0xF0) before and after configure Pass Through ? 

Please advice soon.

Thank you for your advice.

Cheers,

KF Choong

0 Kudos
Reply

675 Views
kfchoong
Contributor IV

Hi Sir / Madam,

I have check the Session Register, NS_REG byte, bit#6 - I2C_LOCKED,  is unable to manually set to 1b with the presence of RF wave on RF interface, but without configure Pass Through. And also without the presence of RF wave on RF interface and PASS THROUGH is NOT configured.  Please see the following 2 experiment results:

Register Byte nameWith no RF presence at RF interface, and Pass Through is NOT configureWith RF presence at RF interface, but Pass Through is NOT configurecomment
Nc_Reg'.' (0x01)'.' (0x01) 
Last_Ndef_Block'\0' (0x00)'\0' (0x00) 
Sram_Mirror_Block'ø' (0xF8)'ø' (0xF8) 
Wdt_Ls'H' (0x48)'H' (0x48) 
Wdt_Ms'\b' (0x08)'\b' (0x08) 
I2c_Clock_Str'.' (0x01)'.' (0x01) 
Ns_Reg'\0' (0x00)'.' (0x01)the bit#6, I2C_LOCKED bit unable to be set to 1b, it still maintained at 0b

Please advice on how to configure or modify the two bits in session register, Byte NS_REG, bit 5 (RF_LOCKED) and bit 6 (I2C_LOCKED).  It is stated that the bit 6 is R&W in I2C interface perspective.

If these bits is not able to set, we are not able to read anything from memory, including the user memory.  I need to gain access, especially to SRAM portion and the mapped SRAM portion when Pass Through is configured, to verify the data is correct.  This is the fastest way now, to write and read back from I2C interface, because I am not able to read using another NFC device, when near field to the RF interface.  NXP hand phone apps is not able to read address page starting from 0xF0.  Thus I am not able to use hand phone to verify it.

Please help.

Thank you for your advice.

Cheers,

KF Choong

0 Kudos
Reply

675 Views
kfchoong
Contributor IV

Hi Sir / Madam,

I have check session register byte#6 -  NS-REG, it seems that the root cause is the memory is lock to RF after configure Pass Through and RF presence.  The following is the experiment result (2nd column):

Register Byte nameAfter configure Pass Through (PTHRU_ON_OFF = 1b)After configure Pass Through (PTHRU_ON_OFF = 1b), then manually set NS_REG byte, bit 6th - I2C_LOCKED = 1b.comment
Nc_Reg'A' (0x41)'A' (0x41) 
Last_Ndef_Block'\0' (0x00)'\0' (0x00) 
Sram_Mirror_Block'ø' (0xF8)'ø' (0xF8) 
Wdt_Ls'H' (0x48)'H' (0x48) 
Wdt_Ms'\b' (0x08)'\b' (0x08) 
I2c_Clock_Str'.' (0x01)'.' (0x01) 
Ns_Reg'!' (0x21)'!' (0x21)the bit#6, I2C_LOCKED bit unable to be set to 1b, it still maintained at 0b

However, I have tried to manually set this I2C_LOCKED bit to 1b.  But the read back still shows 0b. The memory is still lock to RF interface.  Please see column #3, Ns_Reg = 0x21  .

Please advice on how to set this bit.  The datasheet has showed that this bit is R/W from I2C perspective.  But unable to modify it. 

Thank you for your advice.

Cheers,

KF Choong

0 Kudos
Reply

675 Views
kfchoong
Contributor IV

Hi Sir / Madam,

After configure for Pass Through, I can write to SRAM (Block address 0xF8) but unable to read back SRAM (same location).  May I know how can I read back SRAM after configure the Pass Through ?  May I know what are those memories that I can read back after configure for pass through ?  

Thank you.

Cheers,

KF Choong

0 Kudos
Reply