I have a problem when using an ETIMER_1 with DMA on MPC5744P microcontroller. A short description of the system might help you to understand it.
There are mainly 2 input signals produced by 2 mechanical gears with 720 and respectively 60-2 teeth. They are used to determine the speed of a motor and the position of the crankshaft angle. This part works perfectly. I use ETIMER_1 channels 5, 4 and 3 to accomplish this task.
Additionally, the system must produce an electrical signal synchronized with the position of the crankshaft angle of the internal combustion engine. I use ETIMER_1 channel 2 and DMA_0 to do this. Channel 2 counts up to 1440 the rising edges of the 720 teeth gear being reset by channel 3 which is configured to be master. The DMA must push the pattern of the output signal in CMPLD1 and CMPLD2 register whenever the CNTR register reaches the values held in COMP1 and COMP2 register. The OFLAG output signal should be driven on the external pad D configured to be ETC2 output (CTRL2.B.OEN is set somewhere else) . The result should be like it is shown in the attached figure.png (the second row) but it isn’t. Actually I see on the oscilloscope at the beginning a short spike and nothing else afterwards.
This scheme is implemented also on MPC5643L and it works correctly. Almost the same code is implemented on MPC5744P microcontroller making, of course, the required changes especially on the DMA side. An excerpt of the code is given in the attached files (main.c, etimer1.c, dma.c and aips.c).
It seems that DREQ0 and DREQ1 signals produced by the ETIMER are not taken into account by the DMA which does not step through the patterns held in the vectors camAVL_Compare1 and camAVL_Compare2.
I read in some application notes that data cash should be disabled when using DMA transfers but I do not want loose this advantage because the whole application is extremely complex and the execution time is a major requirement.
Another approach is described in AN4856 - MPC574xP SENT/SPC Driver, chapter 3.6 (Memory Allocation). It recommends to create a new region of non-cacheable SRAM memory but the examples are incomplete and I don’t know which impact will have this on the startup code.
Could you help me solve this problem ? Thank you in advance.
Ing. Gelu Movileanu
Senior Software Developer
Original Attachment has been moved to: xSupport.zip