Hello,
I am trying to know what are the reasons, that may cause the offset I am getting from my ADC input.
I am using the code that I wrote (project can be downloaded below). Please check the adc.c and VREF.c files.
I made the small circuit in the Photo (a simple voltage devider) and measured the voltage with two different multimeters. to check the voltage and then compare it with the the adc results. I am always getting an offset of about 2..5mV above the correct voltage.
The ADC0 is configured to 16-bit mode (LSB = 1/ 65535) and the Reference voltage is the internal 1.207 V (also measured with the multimeters). So the error is Delta_Voltage = 1.207V x (300 / 65535) = 5 mV
Some other facts to my ADC configuration :
* I am using the maximal bus clock (60Mhz)
* long sample time
* software trigger
* high speed conversion
I disabled the high speed conversion, but this did not cause any improvement.
I followed the steps in the reference manual for the calibration function.
Any recommendations are welcomed.
Original Attachment has been moved to: ADC_EPWM_VREF.zip
I am now getting better results compared to what I had before(1mV or less below the the measured voltage).
The reason for that is that I was using a very high ADC Clock speed.
I was using the bus frequency as an input frequency for the ADC. ==> ADC_CFG1_ADICLK(0)
(without dividing it : ADC_CFG1_ADIV(0) ==> in this way f_ADCK = f_bus = 60 Mhz )
Now I am still the using the bus frequency as an input frequency for the ADC, but I am deviding it by 8 ==> ADC_CFG1_ADICLK(3) . So f_ADCK = f_bus / 8 = 60 Mhz / 8 = 7.5 Mhz
I fortunately found this note in the ADC conversion time calculator software saying:
NOTE : for best results 16 Bit resoltion rquires ADC CLOCK to be 10 Mhz or lower.
I do not remember reading this note in the reference manual.
Hi anouarraddaoui,
from your schematic it is clear that the VREF output is loaded by R=220+100=320 ohm, considering 1.2V reference, the volatge reference buffer current should be 1.2V/320=3.75mA. Please, check in K22 datasheet (VREF full-range operating behaviors) whether your selected device is able to be loaded with such current. If not (likely), then please increase the resisitors in your divider to follow specification.
regards
R.
Hi anouarraddaoui,
About the ADC CLOCK you can read the datasheet(K22P121M120SF7.pdf), the maximum frequency of 16bit fADCK is 12MHz.
About the ADC accuracy, I recommend you read the AN4373(Cookbook for SAR ADC Measurements):
Best Regards,
Robin
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