I am trying to know what are the reasons, that may cause the offset I am getting from my ADC input.
I am using the code that I wrote (project can be downloaded below). Please check the adc.c and VREF.c files.
I made the small circuit in the Photo (a simple voltage devider) and measured the voltage with two different multimeters. to check the voltage and then compare it with the the adc results. I am always getting an offset of about 2..5mV above the correct voltage.
The ADC0 is configured to 16-bit mode (LSB = 1/ 65535) and the Reference voltage is the internal 1.207 V (also measured with the multimeters). So the error is Delta_Voltage = 1.207V x (300 / 65535) = 5 mV
Some other facts to my ADC configuration :
* I am using the maximal bus clock (60Mhz)
* long sample time
* software trigger
* high speed conversion
I disabled the high speed conversion, but this did not cause any improvement.
I followed the steps in the reference manual for the calibration function.
Any recommendations are welcomed.
Original Attachment has been moved to: ADC_EPWM_VREF.zip