Hi 勇 李,
1. The reset source should be detected as first. You may create separate startup routines for CM, COP and Other reset sources. In that case, please check external RC circuit at RESET pin. The bit capacitance at RESET pin might block correct recognition of reset source. For more details, please check https://community.nxp.com/docs/DOC-103737. The Other reset sources (POR and LVR) could be detected by CRGFLG register.
Note: S12HZ do not have Illegal address reset.
2. Please check capacitance at reset pin according to previous point. Please check whether you defined all three reset vectors. Please, check your configuration for self-clock mode and clock monitor reset (PLLCTL register, CME and SCME bits). Injected high energy into clock circuit might cause a clock lack (depends on circuit parameters and board layout), therefore CM and SCM features was implemented.
Please check also PE7 pin level according to your oscillator settings (Colpitts/Pierce).
3. If you use external watchdog, you should somehow prevent against unwanted MCU reset during MCU programming = when external watchdog is not triggered by MCU. The safest way is mechanical disconnection between external watchdog and MCU RESET pins. The next possible options are inhibiting external watchdog by external voltage or external triggering watchdog during programming. Here it depends on external watchdog features. The internal watchdog is typically inhibited by one of first debuggers command (like “wb 0x03c 0x00 //disable cop”)
I hope it helps you.
Have a great day,
Radek
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
