While researching interrupt logic on the MPC5748G processor, on page 611 in the document MPC5748GRM.pdf, Rev.4, bits in PRC_SEL in register INTC_PSRn are shown to be only 3 bits, but looking at source for examples it appears to be 4-bits and aligned differently. The example code that comes with the S32 Studio, V1.1 has the following configuration so some help here would be appreciated.
From pit.c in hello+pll+interrupt example.
INTC.PSR.B.PRC_SELN = 0x8; /* IRQ sent to Core 0 */
INTC.PSR.B.PRC_SELN = 0x4; /* IRQ sent to Core 1 */
INTC.PSR.B.PRC_SELN = 0x2; /* IRQ sent to Core 2 */