Is PRC_SEL 3 or 4 bits

[CodeWriter]

While researching interrupt logic on the MPC5748G processor, on page 611 in the document MPC5748GRM.pdf, Rev.4, bits in PRC_SEL in register INTC_PSRn are shown to be only 3 bits, but looking at source for examples it appears to be 4-bits and aligned differently.  The example code that comes with the S32 Studio, V1.1 has the following configuration so some help here would be appreciated.

From pit.c in hello+pll+interrupt example.

   INTC.PSR[226].B.PRC_SELN = 0x8;  /* IRQ sent to Core 0 */

   INTC.PSR[227].B.PRC_SELN = 0x4;     /* IRQ sent to Core 1 */

   INTC.PSR[228].B.PRC_SELN = 0x2;     /* IRQ sent to Core 2 */

[alexvinchev · Accepted solution]

clarkkent​,

priority select is 3 bits, but is up-aligned (if I may state it this way), in the MPC documentation "0" is MSB and "15" or "31" is LSB, so PRC_SEL is like it is defined also in the header files (it works this way, checked!):

union {
    vuint16_t R;
    struct {
        vuint16_t PRC_SELN0:1;
        vuint16_t PRC_SELN1:1;
        vuint16_t PRC_SELN2:1;
        vuint16_t  :1;
        vuint16_t  :3;
        vuint16_t SWTN:1;
        vuint16_t  :4;
        vuint16_t PRIN:4;
    } B;
} PSR[1024];

As you see, examples are also correct, they are using bits 0, 1 and 2 (0x8, 0x4, 0x2).