AnsweredAssumed Answered

MPC5554 EQADC Calibration problem

Question asked by DAMIEN WALKER on Jun 30, 2016
Latest reply on Jun 30, 2016 by DAMIEN WALKER

We are having a problem with the EQADC calibration routine.


This uses internally generated 25% and 75% (of VRH-VRL) levels and we are seeing different results between two applications.


In one application, the routine works fine and produces expected values (ie approx. 4K and 12K respectively). However, despite sharing the same software, a second application produces nonsense results (approx. 9K and 10K respectively).


As the 25%/75% levels are generated internally to the uC and the results are not in this ratio, this suggests a  problem with the silicon.


We are aware of e1741 errata note about the 25% level requiring a min of 64 samples and have implemented this.


Is there any known silicon problem that might affect this please or is there any other advice as to what might be causing the problem?


Device topside markings are as follows:

In the working application:





In the non-working application:





Is there a die revision between these two parts for example? Obviously will a BGA package, we cannot easily swap processors!


Many thanks for your help.