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Device Tree Pin Mux Values

Question asked by Simon Locke on Jun 28, 2016
Latest reply on Jul 29, 2016 by Simon Locke
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Hi,

 

I am in the process of porting the iMX6SX Sabre BSP to my own board. However, I have found something that puzzles me in the device tree files for this board.

 

I'm using imx6 4.1.15, and with reference to the kernel source, the file arch/arm/boot/dts/imx6sx-sdb.dtsi contains some fsl,pins entries that have bits set that I cannot explain. For example pinctrl_i2c1 is set to 0x4001b8b1. I can explain bits 0 to 16, but what about the bit at bit 30? With reference to section 35 of the Reference Manual I can map the low 17 bits, but not the top bit.

 

This is also something I can see in other imx6 sabre dtsi files, so there is more to pin muxing than I can see at the moment. I was wondering if because the Reference Manual is generic for all imx6 that it was 'incomplete' depending on the exact silicon. I've looked in the imx6SX data sheet but this doesn't detail any extra information.

 

What am I missing? Can anyone explain these pin-mux values?

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