Issue with the TBI on the BSC9132 processor, no link is active

[jsvholmes]

On the BSC9132 processor the TBI between the eTSEC (eTSEC2) and SerDes (Lane C in SGMII mode) is reporting no active link. I have tried the fix in the errata (A-001487), but the link does not come up. I believe this is causing our packets to never leave the BD and causes a Graceful Stop request to be generated. Is there another step to getting the TBI to link the eTSEC and SerDes that I am unaware of?

[bpe]

TBI is an internal interface between the on-chip PCS and eTSEC. It

acts fully transparently and there is no way to read it's status.

Therefore, I assume the actual problem is missing SGMII link,

which is the SerDes link between the on-chip PCS and the external

device connected to SGMII. The suggestions are as follows:

1. Make sure RCW SerDes configuration options are selected correctly.

   Refer to Section 4.4.16, 4.4.28 of BSC9132RM.

2. Make sure the clock is present on SD_REF_CLKx inputs, it is of the

   correct frequency and satisfies the requirements of the chip

   Hardware Specifications

3. Make sure the signal is present on the corresponding SerDes lane

   and it satisfies the requirements of the chip  Hardware Specifications.

4. Check with the documentation of the external device connected to

   the problematic SGMII interface what type of auto-negotiation it

   supports, if at all.

5. Study NXP appnote AN3869 for details how the on-chip PCS handles

   different types of auto-negotiation over SGMII, make sure your

   software follows the practices the appnote suggests.   Below is the

   link to the appnote:

   https://www.nxp.com/webapp/Download?colCode=AN3869

Regarding errata, the errata list for your chip is still under NDA. Please

creare a Support Case if you wish to discuss errata:

https://community.nxp.com/docs/DOC-329745?sr=search&searchId=125f6419-c9ed-4733-a661-3586d7a392f4&se...

Have a great day,
Platon

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