lpcware

Cortex M0,M3 Interrupt Latency?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by kizerkid on Sat Oct 15 11:13:45 MST 2011
I have tried EXTI (IRQ) Interrupt of LPC1114 (M0-48MHz) and STM32F100 (M3-24MHz) and found some problem about interrupt latency.

From MCU&ARM Documents, I've found that the Interrupt latency of M0 is 16 clocks and M3 is 12 clocks. I try to test their int. latency by out a pulse from one output pin after the EXTI int. is activated by the rising/falling edge  of the input signal on defined EXTI pin. Then I can measure int. latency from the time delay of 1st edge of output pulse after the EXTI input edge.

The result are:  ~1usec for LPC1114(M0) and ~1.8usec for STM32F100(M3)

Are these mean that: LPC1114 has ~48 clock delay = 16 from latency and 32 from some ISR (Interrupt Service Routine) code (may be push, pop etc.)  and STM32F100 also has ~48 clock delay = 12 from latency and 32 from some ISR code ??

I know that, after interrupt is occurred, we must have asm code to push some registers before do any other ISR code...however, I think..is it take all those 32-36 clocks? Is it too much? Actually, my project have to do some process after the rising/falling edge of input signal within ~1.6usec..so..I'm sure that I can't write the code to complete my task within just 0.6usec (for LPC1114)

When I try to see in disassembly panel of CodeRed for any state savingr code after the int. is occured, I just can see about 3-4 lines of asm code for that task..so ..Is it possible that these 3-4 lines take ~32 clock cycles for processing??
Are there any way out to shorten the int. latency? If I write all code in assembly, Can I overcome this problem? (If yes, please give me some example for EXTI Interrupt in asm)

Thank you.

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