Cortex-M3 Pipeline Stalls

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by MikeSimmonds on Sat Aug 09 07:58:10 MST 2014
NOTE: refering the the Cortex-M3 specifically.

Where can I find information about whether LDR instructions cause a stall if the destination register is used in the immediately following instruction -- if indeed this ever occurs. [And other causes of a pipeline stall.]

The exellect book "ARM a system developer's guide" disccuses this issue for ARM9,10,11 cores but
has no information about the Cortex-M3.

I tried reading the Arm Architecture v7M and the Cortex-M3 TRM but didn't get anywhere.

Regards, Mike