lpcware

Secondary Bootloader on Cortex-M0

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 16, 2016 by lpcware
Content originally posted in LPCWare by mmoyano on Thu Jul 01 15:34:27 MST 2010
Hello

Today I am finishing a project based on LPC1113. This hardware needs to update its firmware using the IAP subroutines. I wrote  a secondary bootloader wich size is less than 4KB and it can be stored in the sector 0.
The secondary bootloader is working very well and it can write the user application from sector 1. Below you can see the memory map:

//  ------------------------
// |                        |0x0000 0000
// |    BOOT VECTOR TABLE   |
// |                        |0x0000 00BF
// |------------------------|
// |                        |0x0000 00C0
// |                        |
// |                        |
// |       BOOTLOADER       |
// |                        |
// |                        |0x0000 0FFF
// |------------------------|
// |                        |0x0000 1000
// |   USER VECTOR TABLE    |
// |                        |0x0000 10BF
// |------------------------|
// |                        |0x0000 10C0
// |        JUMPS           |
// |                        |0x0000 12B0
// |------------------------|
// |                        |0x0000 12B4
// |                        |
// |    USER APPLICATION    |
// |                        |
// |                        |
// |                        |
// |                        |
// |                        |
// |                        |
// |                        |0x0000 5FFF
//  ------------------------

Since the Cortex-M0 is not able to change the interrupt vectors, I wrote a code that remaps this vector table to another vector table (USER VECTOR TABLE) from sector 1.
But since in the USER VECTOR TABLE the compiler generates addresses of functions pointing to the interrupt routines, I changed almost all address interrupts in BOOT VECTOR TABLE where each address will be the address of "BRANCHS INSTRUCTIONS" from the user interrupt routine. I call this area as "JUMPS".
So, when an interrupt occurs, the Cortex-M0 takes one address from BOOT VECTOR TABLE that point to one entry in JUMPS and then I wrote assembler code to achieve a branch to the real user interrupt routine that I could be found using the USER VECTOR TABLE.

You can see the attached file with extra info.

Finaly I ran all the code (bootloader + user application) and I found that on each interruptions, the debugger is stopped on IntDefaultHandler, I am assuming that I have a bad address somewhere but anyway, I think that also the stack is changed on each interruptions because in my JUMPS sections, I am changing the LR register and I think that is another possible error for this implementation.

I hope that you can help me with this complex issue.

Thanks in advance!

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