Both cores from SRAM, is it possible?

[lpcware]

Content originally posted in LPCWare by filartrix on Mon Sep 28 04:32:25 MST 2015
My question is: is it possible to run Cortex M4 code from SRAM?
I understand that power consumption when code is executed from SRAM is much lower.
I'm able to have the code of M4 only running from SRAM, and the M0+ running from SRAM, but when I try to use both corese runningfrom SRAM I have issues.
Here's my configuration:
Core M0+ Running from SRAM 1 (32 Kb)
Core M4 sunning from SRAM 0 (64Kb)
The problem is that with Dual core, the code immediately goes in Hard Fault, without even reaching the main()
Code size for both cores is around 40Kb
If I disable  the dual core option, it works!

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Mon Sep 28 15:08:36 MST 2015

First check the MCU Settings memory configuration for both the M4 and M0+ projects to be sure code/data is located and ordered as you expect. Don't forget to check the heap start and stack pointer initialization for each MCU (symbols _pvHeapStart and _vStackTop respectively in each map file). it could be an MCU stack is overwriting RAM some place it shouldn't be.

Thanks and regards,
LPCXpresso Support