LPC11U23 fails to lock PLL with IRC as PLL source

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LPC11U23 fails to lock PLL with IRC as PLL source

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by crawford on Sun Feb 08 16:00:16 MST 2015
I have a custom board with an LPC11U23F and an external 12Mhz crystal. I ran into trouble getting the PLL to lock on the external crystal so I decided to try using the IRC for now. Unfortunately, it seems that it won't lock on the IRC either! I can use the IRC directly as my main clock source, so I know there is nothing wrong with the IRC itself. I'm reasonably sure this is just some silly software misconfiguration but I could use another set of eyes.

This is the (inlined) code that I am using to initialize the clock:
void Chip_SystemInit(void)
{
        /* IRC should be powered up */
        // Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
        LPC_SYSCTL->PDRUNCFG &= ~(1 << 1);
        // Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
        LPC_SYSCTL->PDRUNCFG &= ~(1 << 0);

        /* Set system PLL input to IRC */
        // Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
LPC_SYSCTL->SYSPLLCLKSEL  = 0;
LPC_SYSCTL->SYSPLLCLKUEN  = 0;
LPC_SYSCTL->SYSPLLCLKUEN  = 1;

        /* Power down PLL to change the PLL divider ratio */
        // Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
        LPC_SYSCTL->PDRUNCFG |= (1 << 7);

        /* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz */
        // Chip_Clock_SetupSystemPLL(3, 1);
        LPC_SYSCTL->SYSPLLCTRL = 0x23;

        /* Powerup system PLL */
        // Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
        LPC_SYSCTL->PDRUNCFG &= ~(1 << 7);

        /* Wait for PLL to lock (never locks) */
        // while (!Chip_Clock_IsSystemPLLLocked()) {}
        while ((LPC_SYSCTL->SYSPLLSTAT & 1) == 0);

        ...
}
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by crawford on Sun Feb 15 18:32:19 MST 2015
Well, it turns out there is no functional difference... As it happened, I have a handful of boards that cannot lock the PLL with either code. The board I happened to use for your test worked (and it works for the original code as well). Thanks for removing one of the variables. Now I know that's it's a hardware issue.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by crawford on Sun Feb 15 15:25:38 MST 2015
Fantastic! This works. Thank you.

My code is from LPCOpen 2.03 and it doesn't seem to work. I'm going to dig into this more and figure out the difference.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by R2D2 on Sun Feb 15 14:24:28 MST 2015

Quote: crawford
... a snippet of their initialization code for me to compare against?



LPCOpen init should be a good point to start 

Here's what I'm using for LPC11Cxx 48MHz from IRC:

/* PDRUNCFG register mask */
#if defined(CHIP_LPC11AXX)
#define PDRUNCFGUSEMASK 0x00000D08
#define PDRUNCFGMASKTMP 0x0001E0F7
#elif defined(CHIP_LPC11UXX)
#define PDRUNCFGUSEMASK 0x0000E800
#define PDRUNCFGMASKTMP 0x000005FF
#elif defined(CHIP_LPC1125)
#define PDRUNCFGUSEMASK 0x0000ED00
#define PDRUNCFGMASKTMP 0x000000FF
#else
#define PDRUNCFGUSEMASK 0x0000ED00
#define PDRUNCFGMASKTMP 0x000000FF
#endif


void setup_clock(void)
{
 uint32_t temp;
 //set main clock to IRC
 LPC_SYSCTL->MAINCLKSEL  = 0;
 LPC_SYSCTL->MAINCLKUEN  = 0;
 LPC_SYSCTL->MAINCLKUEN  = 1;
 //PLL source: IRC
 LPC_SYSCTL->SYSPLLCLKSEL  = 0;//IRC
 LPC_SYSCTL->SYSPLLCLKUEN  = 0;
 LPC_SYSCTL->SYSPLLCLKUEN  = 1;
 //power down PLL to change the PLL divider
 temp = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP;
 temp |= ((1<<7) & PDRUNCFGMASKTMP);
 LPC_SYSCTL->PDRUNCFG = (temp | PDRUNCFGUSEMASK);
 //set PLL
 LPC_SYSCTL->SYSPLLCTRL = (3 & 0x1F) | ((1 & 0x3) << 5);
 //power up PLL again
 temp = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP;
 temp &= ~((1<<7) & PDRUNCFGMASKTMP);
 LPC_SYSCTL->PDRUNCFG = (temp | PDRUNCFGUSEMASK);
 //wait until PLL is locked
 while ((LPC_SYSCTL->SYSPLLSTAT & 1) == 0);
 //set clock div
 LPC_SYSCTL->SYSAHBCLKDIV  = 1;
 //Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
 temp = LPC_FMC->FLASHTIM & (~(0x3));
 LPC_FMC->FLASHTIM = temp | 2;
 //set main clock to PLL out
 LPC_SYSCTL->MAINCLKSEL  = 3;
 LPC_SYSCTL->MAINCLKUEN  = 0;
 LPC_SYSCTL->MAINCLKUEN  = 1;
}

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by crawford on Sat Feb 14 22:18:50 MST 2015
I haven't made any headway on this issue. I'm able to reproduce the issue on multiple boards which leads me to believe that it's not a hardware problem. Can anyone post a snippet of their initialization code for me to compare against?
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